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31. 发明专利

JPS55166959A MANUFACTURE OF MIS SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS55166959A
公开(公告)日：1980-12-26
申请号：JP7468479
申请日：1979-06-15
申请人： HITACHI LTD
发明人： UCHIDA KEN
IPC分类号： H01L21/331 , H01L29/73 , H01L29/78
摘要： PURPOSE:To accurately control the impurity doped area of a MIS semiconductor device by doping impurity in a self-alignment by an oxide film etching in the boundary between the thick oxide film for isolating elements and a gate region. CONSTITUTION:An impurity doped region 4 is formed over the drain region 1 and the source region 2 at the end of the gate region 3 between n-type drain region 1 and source region 2. A gate oxide film 6 is formed on the selected portion of one main surface of a p-type semiconductor substrate 5, and a thick oxide films 7, 8 are formed on the other portion. A p-type impurity doped region 4 is formed on the surface of the semiconductor substrate adjacent to the gate oxide film 6 and the thick oxide films 7, 8.

32. 发明专利

JPS5575243A METHOD OF FABRICATING MIS SEMICONDUCTOR DEVICE HAVING TWOOLAYER POLYCRYSTALLINE SILICON WIRED LAYER 失效
公开(公告)号：JPS5575243A
公开(公告)日：1980-06-06
申请号：JP14911178
申请日：1978-12-04
申请人： HITACHI LTD
发明人： UCHIDA KEN
IPC分类号： H01L29/78 , H01L21/3213 , H01L21/768
摘要： PURPOSE:To provide a reliable two-layer polycrystalline silicon wiring layer in a MIS semiconductor device by supplementing the excessively etched portion of an interlayer insulating film occurred upon formation of a connecting opening by simple means. CONSTITUTION:The first polycrystalline silicon electrode 4 is formed on the field and gate oxide films 2 and 3 of a p-type silicon substrate 1, and an opening is formed in the film 3. Then, a gate oxidation thin film 5 and an interlayer insulating thick film 6 are simultaneously thermally oxidized to thereby form the second polycrystalline silicon electrode 7. Since a eaves is made on the electrode 7 by overetching when the films 5 and 6 are etched with the electrode 7 used as a mask, a thermal oxide film 8 is formed on the entire surface to supplement it. When an opening is thereafter formed in the film 8, the surfaces of the substrate 1 and the first electrode 4 are exposed without any eaves to thus complete a reliable two-layer polycystalline silicon wire.

33. 发明专利

JPH069226B2 失效
公开(公告)号：JPH069226B2
公开(公告)日：1994-02-02
申请号：JP3602484
申请日：1984-02-29
申请人： HITACHI LTD
发明人： HAGIWARA TAKAAKI , TANIDA JUJI , MINAMI SHINICHI , NABEYA SHINJI , UCHIDA KEN , YASUI NORIMASA
IPC分类号： H01L27/112 , G11C16/04 , G11C17/00 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792

34. 发明专利

JPH03195057A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03195057A
公开(公告)日：1991-08-26
申请号：JP33272389
申请日：1989-12-25
申请人： HITACHI LTD
发明人： UCHIDA KEN , MINAMI SHINICHI , KAMIGAKI YOSHIAKI , FURUSAWA KAZUNORI , TAKESHITA MASANOBU
IPC分类号： H01L21/8234 , H01L27/088
摘要： PURPOSE:To realize an extra-fine and highly integrated circuit by a method wherein high impurity concentration regions of which an NMOS element and/or source and drain regions of the NMOS are composed in a high breakdown strength are formed by utilizing source and drain electrode lead apertures. CONSTITUTION:N-type impurity is implanted by using a gate electrode 13 as a mask to form n -type impurity regions 11a and n-type impurity is implanted again through contact holes 14a drilled in a silicon oxide film 14 to form n -type impurity regions 11b. Then a source lead electrode and a drain lead electrode 15 and 15 are formed. Therefore, the source and drain lead electrodes 15 are brought into contact with the n -type impurity regions 11b in a self-alignment manner. Moreover, the source and drain lead electrodes 15 and the high impurity concentration regions 11b can be formed in one photolithography process, so that a margin for the discrepancy of mask alignment can be reduced. With this constitution, an extra-fine and highly integrated circuit can be realized.

35. 发明专利

JPH022131A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH022131A
公开(公告)日：1990-01-08
申请号：JP14617888
申请日：1988-06-13
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MEGURO HIDEO , YOSHIURA AIMEI , ITAGAKI TATSUO , UCHIDA KEN
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To prevent resistance at electrode of an element from increasing and enhance peeling resistance of bump electrode by directly forming a wiring layer of a semiconductor integrated circuit with the bump electrode on an interlayer insulation layer at the ground pad part of the bump electrode through a barrier metal at an area which becomes the electrode pat of the element. CONSTITUTION:A wiring layer 12 consisting of aluminum or its alloy is patterning formed so that wiring part between elements may be formed together along with an electrode part 12A of a MOS transistor Qn and a ground pad part 12B of a bump electrode 16. The wiring layer 12 is isolated from a semiconductor substrate 1 at a part which becomes the electrode 12A of an element by a barrier metal 10 consisting of a high melting-point metal or its compound and is formed directly on a silicon interlayer insulation layer 8B at a part which becomes a ground pad part 12B of the bump electrode 16. It prevents electrode resistance from increasing at the electrode part 12A of the element due to deposition of silicon and enhances peeling resistance of the bump electrode 16 since no barrier metal 10 with a weak adhesion strength exists for the insulation layer 8B at the ground pad part 12B of the bump electrode 16.

36. 发明专利

JPH01109763A SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01109763A
公开(公告)日：1989-04-26
申请号：JP26643987
申请日：1987-10-23
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKUYAMA KOSUKE , UCHIDA KEN , KUSUYAMA KOICHI , MEGURO SATOSHI , KATTO HISAO , KOMORI KAZUHIRO
IPC分类号： H01L21/8246 , H01L27/112
摘要： PURPOSE:To improve a degree of integration, by introducing impurities into the main surface part of a substrate beneath a gate electrode of first layer through the gate electrode of first layer, writing information, and alternately forming gate electrodes of second and third layers respectively between the gate electrodes of first layer. CONSTITUTION:Gate electrodes of first layer 5 of a vertical mask ROM are formed. Thereafter, information writing impurities 6a are introduced into the main surface part of a substrate beneath the gate electrodes of first layer 5 through the gate electrodes of first layer 5. Then information is written. The information writing in memory cells Q1, Q3, Q5 and Q7 composed of the gate electrodes of first layer 5 are performed in a self-aligning mode with respect to the gate electrodes of first layer 5. Gate electrode of second and third layers 9A and 9B are alternately formed between the gate electrodes of first layers 5. Thus the gate electrodes 9A and 9B of second and third layers are overlapped, and separating sizes between both electrode layer on the gate electrode of first layers 5 can be eliminated. In this way, the area for the memory cells can be reduced, and the degree of integration of the vertical mask ROM can be improved.

37. 发明专利

JPS63122163A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63122163A
公开(公告)日：1988-05-26
申请号：JP26753386
申请日：1986-11-12
申请人： HITACHI LTD
发明人： SHIBATA TAKASHI , UCHIDA KEN , TAKEDA TOSHIFUMI , MATSUMOTO YOICHI
IPC分类号： H01L29/78 , H01L21/8246 , H01L27/112
摘要： PURPOSE:To reduce the creeping phenomenon of a low-concentration region into a channel region, to prevent a short-channel effect and to enhance the characteristic by a method wherein the low-concentration region on the side of the channel region of a drain is formed by impurities of a small diffusion-coefficient. CONSTITUTION:An N-channel MISFET acting as a memory cell is composed of the following: a gate-insulating film 9 composed of a silicon oxide film formed by the thermal oxidation of the surface exposed from a field insulating film 7 of a semiconductor substrate 1; a gate electrode 10 which is composed of a polycrystalline silicon film formed, e.g., by a CVD method and is constructed by laminating a refractory metal film of, e.g., Mo, W, Ta, Ti or the like or a silicide film of this metal on it; an n-type semiconductor region (low-concentration region) 11 constituting the side of a channel region of a source-drain region; an n type semiconductor region (high- concentration region) 12 constituting the part which is separated from the channel region. The n-type semiconductor region 11 is composed of n-type impurities of a small diffusion-coefficient, e.g., arsenic (As), and its dose quantity is set at about 1X10 atoms/cm . By using the arsenic, a creeping phenomenon under the gate electrode is reduced so that a short-channel effect can prevented.

38. 发明专利

JPS62193137A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62193137A
公开(公告)日：1987-08-25
申请号：JP3295786
申请日：1986-02-19
申请人： HITACHI LTD
发明人： HARA YUJI , UCHIDA KEN , KATSUTO HISAO , NAGASAWA KOICHI , MIYAMOTO KEIJI
IPC分类号： H01L21/66 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To perform bonding after probe check at high reliability, by using a plurality of measuring electrodes, which are provided on a semiconductor substrate, measuring the electric characteristics of a semiconductor device, and thereafter removing the measuring electrodes. CONSTITUTION:A tester probe P is contacted with the surface, which is exposed in a hole 12 in a probe checking pad 10P, and probe checking is performed. The probe checking pad 10P is provided in a region, where semiconductor elements such as an MISFET and the like are not provided, at the peripheral part of a chip 1, i.e., on a field insulating film 2. Therefore, the semiconductor elements such s the MISFET are not damaged by the probe P. Then, an insulating film 13 comprising a silicon nitride film is formed on the entire surface of the substrate 1 by a plasma CVD method. The probe checking pad 10P is covered with the insulating film 13. Then the end part of the pad 10P or the insulating films 11 and 13 at a part of a wiring 10, which is connected to said end part, are selectively removed, and a connecting hole 14 is formed. Thus the reliability in bonding can be enhanced.

39. 发明专利

JPS60182173A VOLTAGE IMPRESSING CIRCUIT 失效
公开(公告)号：JPS60182173A
公开(公告)日：1985-09-17
申请号：JP3602484
申请日：1984-02-29
申请人： HITACHI LTD
发明人： HAGIWARA TAKAAKI , TANIDA YUUJI , MINAMI SHINICHI , NABEYA SHINJI , UCHIDA KEN , YASUI NORIMASA
IPC分类号： H01L27/112 , G11C16/04 , G11C17/00 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To impress voltage without erroneous writing or erasing by a method wherein, after impressing a specified node with power supply voltage, multiple nodes are impressed with high voltage in a 5V single power supply EEPROM. CONSTITUTION:A voltage impressing circuit is composed by means of connecting an MNOS element comprising a gate 3, a drain 5 and a substrate 7 to a high voltage decoder 102 which grounds or boosts voltage up to high voltage VP (voltage of node 110) utilizing a transistor 103 impressed with power supply voltage, a boosting circuit 101 and input signals B-D. In case of writing in, firstly impress an input signal A with high voltage (VCC) (this may be performed after input signal C) and impress another input signal C with high voltage and then impress the other signal B with high voltage. The other input signal D shall be constantly grounded.

40. 发明专利

JPS57176743A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS57176743A
公开(公告)日：1982-10-30
申请号：JP6120481
申请日：1981-04-24
申请人： HITACHI LTD
发明人： KOMORI KAZUHIRO , SUGIURA JIYUN , UCHIDA KEN
IPC分类号： H01L27/112 , H01L21/3205 , H01L21/76 , H01L21/8246 , H01L21/8247 , H01L23/52 , H01L27/105 , H01L29/788 , H01L29/792
摘要： PURPOSE:To obtain a semiconductor memory capable of microminiaturization and having preferable characteristics by separating an area of MISFET rows via semiconductor or conductor layers of the prescribed potential. CONSTITUTION:Rows of MISFET3 forming a memory array are formed on a gate oxidized film 2 on a P type silicon substrate 1, and polycrystalline silicon layers 4 are formed between the rows. A polysilicon floating gate 5 perpendicularly crossing the layer 4 and a control gate 6 as a word line are formed on the film 2 between the layers 4, and the intermediate between the gates become N type source or drain region 7. The layer 4 is secured to a potential (ground level) not inverted at the surface of the semiconductor substrate under the layer 4, thereby the transistor groups can be isolated from each other.

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