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31. 发明专利

JPH0415006A DESK WITH DISPLAY FUNCTION SPECIAL FOR INFORMATION PROCESSOR 失效
公开(公告)号：JPH0415006A
公开(公告)日：1992-01-20
申请号：JP11761090
申请日：1990-05-09
申请人： HITACHI LTD
发明人： KOBAYASHI MASAMITSU , YAMAOKA HIROMASA , TAKAKURA MITSUO
IPC分类号： A47B13/00 , A47B13/12 , A47B21/00 , A47B37/00
摘要： PURPOSE:To efficiently use the desk space by embedding a plane display on the desk, opening a slide-type shielding plate when an information processor is used, and closing the same when it is not used. CONSTITUTION:A desk in the title comprises a desk 1, a plane display 2, a glass 3 and a slide-type shielding plate 4. When an information processor is not used, a display portion is shielded by the slide-type shielding plate 4, and when it is used, shielding is canceled. When the information processor is not used, the desk top surface uses a transparent substance such as glass or the like in order to fulfil the function as the desk. When the desk top surface is glass, however, a problem is caused by reflection of light when the desk is used as a desk, so that only a display portion is made transparent, and when it is not used, the display portion is also made not to be transparent by using a slide type shielding plate.

32. 发明专利

JPH02244739A METHOD AND DEVICE FOR REALIZING COMBINATION CIRCUIT 失效
公开(公告)号：JPH02244739A
公开(公告)日：1990-09-28
申请号：JP6369489
申请日：1989-03-17
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： OHASHI AKIHIRO , WATABE RYUICHI , YAMAOKA HIROMASA , IGARI KUNIYUKI , ISAKA YOSHINOBU
IPC分类号： G06F7/00 , G06F7/76 , H01L21/82 , H01L21/8247 , H01L29/788 , H01L29/792
摘要： PURPOSE:To realize a combination circuit which can be changed easily by using an non-volatile memory which can be rewritten by adding a non-volatile memory control part which controls input/output signal of the non-volatile memory to the non-volatile memory. CONSTITUTION:When an input signal enters an EPROM1, an input latch 25, and a comparison circuit 26, the EPROM1 outputs data being based on the input signal. Also, the comparison circuit 26 outputs a signal only when the input latch value differs from the input signal. The output from the comparison circuit 26 is the reading timing signal of the input latch 25 and when also becomes the data-reading timing signal of an output latch 28 through a one-shot 27. Thus, only when the input signal differs from the value of the input latch 25, a new data is latched in the input latch 25 and the output latch 28. Therefore, only when the input signal differs from the previously input signal, a new data is latched at the output latch 28.

33. 发明专利

JPS62245360A DUPLICATED SWITCHING DEVICE FOR MULTICONTROLLER SYSTEM 失效
公开(公告)号：JPS62245360A
公开(公告)日：1987-10-26
申请号：JP8798886
申请日：1986-04-18
申请人： HITACHI LTD
发明人： SAITOU SUMIHISA , AMAHI YASUHIRO , YAMAOKA HIROMASA , SHIMOYAMA KAZUHIKO
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To complete a switching without affecting realtime controllability, by diagnosing a working system and a standby system, and performing the switching instantly by a hardware circuit. CONSTITUTION:Controllers C1 and C1' are connected to a data transmission equipment 10 through data memories M1 and M1'. And a duarized system is constituted so that the controller C1 and the data memory M1 construct the working system, and the controller C1' and the data memory M1', the standby system. A duarized switching circuit 1 diagnoses the working system and the standby system, and write control circuits 21, and 31 transcribe the content of the output area of the working system when the working system is operated normally. And switching is performed so that the duplicated switching circuit 1 interrupts a transcription when certain abnormality is generated in the working system, and the standby system takes over a process.

34. 发明专利

JPS62171002A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS62171002A
公开(公告)日：1987-07-28
申请号：JP1192386
申请日：1986-01-24
申请人： HITACHI LTD
发明人： ICHIKAWA TETSUO , SHIMOYAMA KAZUHIKO , SATO TOMOKATSU , YAMAOKA HIROMASA , TAKAKURA MITSUO
IPC分类号： G06F9/34 , G05B19/02 , G05B19/05
摘要： PURPOSE:To facilitate programming by selecting either one of address modifying registers or both registers with the aid of a bit installed on an instruction code part. CONSTITUTION:Prior to executing word processing requiring address modification or a bit processing instruction, an address modification amount for each processing is stored in a word processing address register 25 and a bit processing address register 26. When a multiplexer 27 fetches instructions from a program memory 2, selects and judges that it uses either one of the registers 25 and 26 or neither of them, according to the bit lying in the instruction code part of the instruction concerned, it adds the address part of the instruction fetched from the memory 2 to the address modification amount or '0' (no modification), which is stored in the selected register, and takes the added one for an operand address at the time of executing the instruction. Thus the designation of the register becomes unnecessary, thereby facilitating programming.

35. 发明专利

JPS6292732A BATTERY BACK-UP APPARATUS OF CONTROLLER 失效
公开(公告)号：JPS6292732A
公开(公告)日：1987-04-28
申请号：JP22873085
申请日：1985-10-16
申请人： HITACHI LTD
发明人： KURISU YOFUMI , YAMAOKA HIROMASA
IPC分类号： G01R31/36 , H02J7/00

36. 发明专利

JPS626304A CENTRAL PROCESSING UNIT FOR SEQUENCE CONTROL 失效
公开(公告)号：JPS626304A
公开(公告)日：1987-01-13
申请号：JP14477885
申请日：1985-07-03
申请人： HITACHI LTD
发明人： YAMAOKA HIROMASA , OKAMOTO TADASHI , AZUSAWA NOBORU , MIURA KIYOSHI
IPC分类号： G05B19/05 , G05B19/02
摘要： PURPOSE:To increase the processing speed of a central processing unit for sequence control by providing a shift register and an arithmetic means for adjacent column bits, etc. and to perform the inter-bit operation even the blocks of the divided columns are connected to each other. CONSTITUTION:A central processing unit 1 for sequence control is provided with a program memory 12, a program counter 13, a program controller 15 and a clock generating part 14 together with an input inverting part 111, an inter-column bit computing element 113, an accumulator 114, an output gate 115, an AND computing element 117 and a shift register 130. The register 130 supplies and stores successively the bit output 232 of the 4th column of a computing element 113 and delivers the storage value of the same row preceding just one block. Thus it is possible to attain the OR connection (operation of a short bar) between blocks divided by the ladder sequence control without using any working memory. Then the 1:1 correspondence is secured between the picture information and the program information.

37. 发明专利

JPS61267161A TRANSFERRING DEVICE FOR MULTIPLE SYSTEM DATA 失效
公开(公告)号：JPS61267161A
公开(公告)日：1986-11-26
申请号：JP10821085
申请日：1985-05-22
申请人： HITACHI LTD
发明人： KURISU YOFUMI , YAMAOKA HIROMASA
IPC分类号： G06F13/36 , G06F11/20 , G06F15/16 , G06F15/167
摘要： PURPOSE:To eliminate a transfer waiting time and to realize the highly speedy transfer at the time of competition by executing the transferring by using the direct bus at the time of the bus empty condition of the transferring destination control system and executing the transferring to the dual port memory at the time of using the bus. CONSTITUTION:The data transfer request from respective control systems is started to a bus occupying device 12, and when the bus at the transfer destination is empty in accordance with the using condition of buses 3a and 3b, a bus occupying action is executed, an occupying signal 14, or a bus occupying abandoning signal 15, when the bus is used, is outputted to a bus control device 13. The bus control device 13, when the bus occupying is obtained, releases a direct bus 10 with a gate control function by a signal 18 and links respective control systems 3a and 3b. At the time of occupying and abandoning the bus, a dual port memory 4 is started by a signal 19, and the control system having the transferring request transfers the data to the section of the dual port memory 4. The control system of the transferring destination executes periodically the data transferring at the section of the dual port memory 4.

38. 发明专利

JPS61190603A MULTIPROGRAMMABLE CONTROL DEVICE 失效
公开(公告)号：JPS61190603A
公开(公告)日：1986-08-25
申请号：JP2943685
申请日：1985-02-19
申请人： HITACHI LTD
发明人： SASAKI WATARU , OKAMOTO TADASHI , YAMAOKA HIROMASA , SHIMOYAMA KAZUHIKO
IPC分类号： G05B19/05
摘要： PURPOSE:To rationalize the capacity of a memory by providing the memory of a data link device with an address conversion mechanism for addressing of this memory. CONSTITUTION:A programmable controller (PC) 210 is constituted with an essential PC consisting of CPU211, a main memory 211A, an I/O 212, and a common bus 213, a bus interface 214, and the data link device consisting of a connecting circuit 215 and a link data storage part 218. This link data storage part 218 is provided with a memory 216 for buffer and an address conversion mechanism 217. The address conversion mechanism 217 performs the address conversion for correspondence between addresses on a bus 219 and addresses of the main memory 216. In this address conversion, a block to which a given input/output address belongs is discriminated, and an address of the main memory 216 to which this block corresponds is calculated.

39. 发明专利

JPS6079431A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS6079431A
公开(公告)日：1985-05-07
申请号：JP18583283
申请日：1983-10-06
申请人： HITACHI LTD
发明人： OKAMOTO TADASHI , SHIMOYAMA KAZUHIKO , YAMAOKA HIROMASA , TAKAKURA MITSUO
IPC分类号： G05B19/05 , G06F9/32 , G06F9/35 , G06F9/355
摘要： PURPOSE:To improve a processing speed by discriminating between a register modification addressing mode and a direct addressing mode from the instruction out of a memory, and reading an operand without passing it through an arithmetic circuit when the latter is discriminated. CONSTITUTION:Instruction resisters 11 and 18 provided to a CPU1 are provided with operand look-ahead permitting signal parts POF, and the register 11 and an arithmetic circuit 7 are connected to a process input device 13 through a switch 27. When an instruction read out of a memory 12 for program storage by a program counter 4 and latched in the register 11 is in direct address mode, the switch 27 is operated with the signal part POF to read an operand from the device 13 directly; and the operand is latched in a register 26 with an arithmetic end signal 104 and the instruction is transferred from the resiter 11 to the register 18 to perform specific arithmetic through a control circuit 3 and the arithmetic circuit 7.

40. 发明专利

JPS5745653A Multiplex output collation system 失效
标题翻译：多输出输出系统
公开(公告)号：JPS5745653A
公开(公告)日：1982-03-15
申请号：JP12108280
申请日：1980-09-03
申请人： Hitachi Ltd
发明人： YAMAOKA HIROMASA , IWASA YUUZABUROU
IPC分类号： G06F11/18 , G06F11/16 , G06F13/00 , G06F15/16 , G06F15/177
CPC分类号： G06F11/167
摘要： PURPOSE:To process the collation of multipoint data with one data collation set, by making collation through the readout of the content of registers which are accessible, and transmitting the coincidence data as the address for the counter value to the output device. CONSTITUTION:Data outputted from each duplex CPU(not shown) via buses 101, 102 are inputted to registers 51, 52. The write-in address of the data section is designated with the address of the buses 101, 102 and the readout address of data is designated with the value of a counter 53. The data of the registers 51, 52 designated with the counter 53 is collated 54, and only when they coincide, the data is outputted to a bus 103 by taking the value of the counter 53 as the address section. If uncoincidence of data has been observed for longer than a prescribed time, an error signal is transmitted.
摘要翻译：目的：通过对可访问的寄存器的内容的读出进行排序，并将符合数据作为计数器值的地址发送到输出设备，来处理多点数据与一个数据对照集的对照。构成：经由总线101,102从每个双工CPU（未示出）输出的数据被输入到寄存器51,52。数据部分的写入地址由总线101,102的地址和用计数器53的值指定数据。用计数器53指定的寄存器51,52的数据被对照54，并且只有当它们一致时，通过取计数器53的值将数据输出到总线103 作为地址部分。如果观察到数据的长度超过规定时间，则发送错误信号。

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