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31. 发明专利

JP2510605B2 失效
公开(公告)号：JP2510605B2
公开(公告)日：1996-06-26
申请号：JP18332287
申请日：1987-07-24
申请人： HITACHI LTD
发明人： ARA MARI , SAWAMOTO HIDEO , YAMAGATA MAKOTO
IPC分类号： G06F9/46 , G06F12/10

32. 发明专利

JPH0444131A DEVICE AND METHOD FOR EXECUTION OF INTER-PROCESSOR COMMUNICATION IN PLURAL OS RUNNING SYSTEMS 失效
公开(公告)号：JPH0444131A
公开(公告)日：1992-02-13
申请号：JP14999190
申请日：1990-06-11
申请人： HITACHI LTD
发明人： TANAKA TOSHIHARU , UMENO HIDENORI , INOUE TARO , HARAGUCHI MASATOSHI , YAMAGATA MAKOTO
IPC分类号： G06F15/16 , G06F9/46 , G06F15/177
摘要： PURPOSE:To eliminate the delay of an external interruption due to an SIGP instruction of an inter-processor communication instruction by detecting the holding of the external interruption by a decision means and at the same time carrying out the external interruption in response to a fact that a running virtual processor can have an external interruption. CONSTITUTION:A decision means 150 decides periodically the presence or absence of an external interruption held by a running virtual processor and then detects the holding the external interruption through a real processor 100. At the same time, an execution means 170 applies an external interruption to the virtual processor in response to a fact that the running virtual processor can have an external interruption. Thus it is possible to obtain a practicable virtual computer system for the virtual processor without delaying unreasonably the external interruption due to an SIGP instruction and with no intervention of a virtual computer control program.

33. 发明专利

JPH02294713A TOD COUNTING SIGNAL GENERATING CIRCUIT 失效
公开(公告)号：JPH02294713A
公开(公告)日：1990-12-05
申请号：JP11494589
申请日：1989-05-10
申请人： HITACHI LTD
发明人： YAMAGATA MAKOTO , ISHIKAWA SUKETAKA
IPC分类号： G06F1/14
摘要： PURPOSE:To obtain a group of counters whose updating time is completely the same by mutually transferring a synchronizing signal synchronized by a synchronizing circuit between its own system and the other system, and selecting and outputting a signal outputted first out of synchronizing signals from the self-system and the other system as a synchronizing signal for updating a TOD counter. CONSTITUTION:Both the systems are respectively provided with synchronizing circuits 12, 22 to be driven by a common clock 1, and time-of-day (DOD) count signal forming circuits 10, 20 which synchronizes synchronizing signals with nearly constant period sent from the other and its own systems and generates a synchronizing signal, are respectively provided with synchronizing signal sending circuits. The synchronizing signal sending circuits mutually send synchronized synchronizing signals and each of them selects and outputs a synchronized signal output first out of the synchronizing signals in the its own system and the other system as the updating signal of the TOD counter and updates the TOD counter by the updating signal. Consequently, even when a circuit has plural synchronizing circuits, their updating time can be allowed to coincide and all TOD values can always be allowed to coincide with each other.

34. 发明专利

JPH01255945A ADDRESS CONVERTER IN VIRTUAL COMPUTER 失效
公开(公告)号：JPH01255945A
公开(公告)日：1989-10-12
申请号：JP8292188
申请日：1988-04-06
申请人： HITACHI LTD
发明人： YAMAGATA MAKOTO , SAWAMOTO HIDEO , UMENO HIDENORI
IPC分类号： G06F9/46 , G06F12/10
摘要： PURPOSE:To decrease an address converting overhead by holding, on a TLB, the TLB entry of the more number of guests than the number of identifiable guests by a virtual machine identifier (VM identifier) on an address converting buffer (TLB) without changing an interface with software. CONSTITUTION:At the time of an ordinary guest, the VM identifier of a TLB 1 and the VM identifier of the guest during the travelling are compared. On the other hand, in case of a DATOFF guest, a control block address stored in a space identifier field 6 of the TLB 1 and the control block address of the guest during the travelling are compared. In this case, the value common to respective DATOFF guests is stored in a VM identifier field 5 of the TLB 1. Thus, in case of the DATOFF guest, by identifying the guest with the space identifier field 6, more guests can be identified.

35. 发明专利

JPS63208148A CHANNEL CONTROLLER 失效
公开(公告)号：JPS63208148A
公开(公告)日：1988-08-29
申请号：JP4021187
申请日：1987-02-25
申请人： HITACHI LTD
发明人： NINOMIYA KAZUHIKO , YAMAGATA MAKOTO
IPC分类号： G06F13/12
摘要： PURPOSE:To improve the independence of a channel device by providing plural data buffer registers, all allocating selectively the data buffer register of an unused state, when a memory access request from the channel device has been received. CONSTITUTION:When a channel device 100 executes an input/output operation by a write command, the channel device 100 requests data transfer to a channel controller 200. The channel controller 200 receives data transfer request from the channel 100, when one of buffer registers 220-222 is in an unused state. At the time of requesting data transfer from the device 100, when all of the registers 220-222 are in an unused state, the channel controller 200 allocates the data buffer register 220 to the channel 100, as a use state by a data transfer request by the channel 100, and requests data fetching to a memory device 300. When a fetching operation is completed, the memory device 300 loads fetch data onto a bus 320, and also, informs a memory access completing signal to the device 200.

36. 发明专利

JP2012146041A Computer device and signal transmission method 审中-公开
标题翻译：计算机设备和信号传输方法
公开(公告)号：JP2012146041A
公开(公告)日：2012-08-02
申请号：JP2011002647
申请日：2011-01-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMAUCHI TATSUYA , KOBAYASHI MASAHIRO , YAMAGATA MAKOTO , TAMURA TAKASHI , WATANABE KENICHI
IPC分类号： G06F3/00 , H03M7/14
CPC分类号： G06F13/4282 , G06F2213/0026
摘要： PROBLEM TO BE SOLVED: To suppress generation of a random pattern signal in long-distance data transmission surpassing the PCIe interface specification, without using a sideband signal.SOLUTION: In the transmission method which includes a first component having at least a physical layer of PCIe specifications, a second component having at least the physical layer of PCIe specifications, and a transmission line for connecting between the first and the second components, and transmits a PCIe signal between the first and the second components; EI alternate signals which can be transmitted by the physical layer of PCIe specifications continue to be transmitted as an alternative to the Electrical Idle (EI) state defined by the PCIe specifications.
摘要翻译：要解决的问题：在不使用边带信号的情况下，抑制超过PCIe接口规范的长距离数据传输中的随机模式信号的产生。解决方案：在包括具有至少PCIe规格的物理层的第一组件的传输方法中，至少具有PCIe规格的物理层的第二组件和用于在第一组件和第二组件之间连接的传输线并且在第一和第二组件之间发送PCIe信号; 可以由PCIe规范的物理层传输的EI交替信号继续作为PCIe规范定义的电气空闲（EI）状态的替代传输。版权所有（C）2012，JPO＆INPIT

37. 发明专利

JP2003114802A PROCESSOR 审中-公开
公开(公告)号：JP2003114802A
公开(公告)日：2003-04-18
申请号：JP2001308255
申请日：2001-10-04
申请人： HITACHI LTD
发明人： IMORI HIROMITSU , YAMAGATA MAKOTO
IPC分类号： G06F9/38 , G06F9/46 , G06F9/48 , G06F11/30
摘要： PROBLEM TO BE SOLVED: To prevent unnecessary system failure and enhance reliability of the system. SOLUTION: Assuming that a unit 101 requests a unit 102 to execute a store instruction and requests a unit 103 to execute a rfid instruction for switching from an OS to a user program (UP), the unit 103 causes a register 106 to have an identification bit 114 of '1' (UP) and notifies a circuit 107 of the execution of the rfid instruction. The circuit 107 sets a flag 108 and sets a register 109 to '0'. The value of the register 109 is added by a +1 circuit 110, and compared with the value of a register 112 by an identity circuit 111. When the values are identical, the circuit 107 resets the flag 108 to '0'. A failure notice is given from the unit 102 to the unit 104 and the circuit 107, and thereby, when the flat 108 is '1', the circuit 107 sets a flag 113 to '1' as failure during surveillance. Otherwise, the flag 113 is set to '0'. When the flag 113 is '1', the failure is handled as occurring in the OS. When the flag 113 is '0', the failure is handled as occurring in the UP.

38. 发明专利

JP2001267890A CLOCK GENERATION DEVICE, BUS INTERFACE CONTROLLER AND INFORMATION PROCESSOR 失效
公开(公告)号：JP2001267890A
公开(公告)日：2001-09-28
申请号：JP2000080738
申请日：2000-03-22
申请人： HITACHI LTD
发明人： YAMATO AKIHIRO , YAMAGATA MAKOTO , YAMAMOTO TAKASHI , SHIMODA TERUAKI
IPC分类号： G06F13/42 , G06F1/08 , G06F1/10 , G06F1/12 , H03K5/00 , H03K5/04
摘要： PROBLEM TO BE SOLVED: To mount plural clock systems with respect to an inner clock and an outer unit only by the distribution system of an inner clock one system and to control frequency conversion only by a logic circuit. SOLUTION: A processor system 21 has a means 25 for generating a reference synchronizing signal for synchronization in the pertinent device from a reference clock for synchronization with peripheral equipment and generating an inner operation clock. The means generates the inner clock by changing the duty of respective clock cycles. A bus access timing signal generation circuit 24 sets the reference synchronizing signal as a reset signal, has a synchronous counter deciding the number of counts by a frequency ratio which is previously set and generates the access timing signal with peripheral equipment. A bus input/output signal conversion circuit 23 synchronously accesses plural processors having clock systems operating at plural different speeds such as an outer bus by setting the access timing signal as the enable signal of the enable latch of an outer interface.

39. 发明专利

JP2000242679A DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2000242679A
公开(公告)日：2000-09-08
申请号：JP4262299
申请日：1999-02-22
申请人： HITACHI LTD
发明人： KIKUCHI ATSUSHI , SASAKI TETSUO , MINOHARA KAZUHIKO , HASHIMOTO TORU , YAMAGATA MAKOTO
IPC分类号： H01L21/82 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a design method for preparing a semiconductor integrated circuit capable of reducing the increase in a chip area and of carry out a fast operation. SOLUTION: In inter-block wiring deign 104, an inverter insertion number to be inserted to wiring between function blocks is obtained based on a wiring length between the function blocks and the allowable amount of wiring delay time and a file for indicating the correspondence of inter-block wiring to the inverter insertion number is prepared. A function logic description file is prepared in logic input 105 and a gate circuit corresponding to each of the function blocks is generated based on the function logic description file and a result obtained in timing budget design 103 in logic synthesis 106. The file obtained in the inter-block wiring design is added to input and the gate circuit corresponding to the function block provided with a polarity inverted output terminal is generated. Further, a relay inverter closest to the polarity inverted output terminal is added to the gate circuit by considering an insertion interval and output is performed as a function block file.

40. 发明专利

JP2000181794A FAULT PROCESSING SYSTEM FOR INSTRUCTION PROCESSOR 失效
公开(公告)号：JP2000181794A
公开(公告)日：2000-06-30
申请号：JP36029398
申请日：1998-12-18
申请人： HITACHI LTD
发明人： JIN KENJI , YAMAGATA MAKOTO , IMORI HIROMITSU
IPC分类号： G06F12/08 , G06F12/16
摘要： PROBLEM TO BE SOLVED: To make an intermittent/fixed judgement and to secure the reliability while maintaining the performance of the whole device without disconnecting a memory in case of an intermediate fault by handling a fault as a fixed fault only when a fault frequency reaches a certain value. SOLUTION: The fault caused in a WAY0 is reported to a fault frequency counter 10 and a memory control circuit 9 since no retrieval data sequence is present in a WAY1. At this time, the count of the fault frequency counter 10 is set to one. Then data are rewritten and then a parity check is made; if a fault is reported even at this time, the fault frequency counter 10 further counts up by one and an indication for data rewriting is sent again from the memory control circuit 9. If data rewriting and a parity check are carried out four times and a fault is detected in a 5th check, a fixed fault is judged here for the 1st time and the memory is disconnected. Consequently, the reliability of the whole device can be maintained by slightly increasing the circuit scale.

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