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31. 发明专利

JPH1125604A MAGNETIC DISK DEVICE AND SEMICONDUCTOR DEVICE USING THE DEVICE 失效
公开(公告)号：JPH1125604A
公开(公告)日：1999-01-29
申请号：JP17352997
申请日：1997-06-30
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , KOBAYASHI NAOYA , MORIYASU TAKASHI
IPC分类号： G11B20/10 , G11B20/14 , G11B20/18
摘要： PROBLEM TO BE SOLVED: To regulate continuity of 0 or 1 in recording codes by performing set partition in an n-bit unit into output groups of 1st and 2nd signal converting circuits. SOLUTION: Since output signal groups of two RS inspection code arithmetic circuits 3-2 and 3-4 are not restricted in continuous numbers, these output signals are not digitally recordable, and are inputted to an 8-9 converter circuit 3-5. In this circuit, an output of 9 bits is given to an input of 8 bits, and an output bit string is not continued to be >=4 pieces of 0 or 1 by this conversion. When this output signal group is encoded for set partition, the continuous number of pieces of o or 1 is

32. 发明专利

JP2559457B2 失效
公开(公告)号：JP2559457B2
公开(公告)日：1996-12-04
申请号：JP9153288
申请日：1988-04-15
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , KATAYAMA HITOSHI
IPC分类号： G11B5/09 , G11B5/024 , G11B5/53

33. 发明专利

JP2523554B2 失效
公开(公告)号：JP2523554B2
公开(公告)日：1996-08-14
申请号：JP30123686
申请日：1986-12-19
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , SAWAMURA HIDEHIKO
IPC分类号： G11B5/09 , G11B20/14

34. 发明专利

JPH08147611A METHOD AND APPARATUS FOR MAGNETIC RECORDING AND REPRODUCING 失效
公开(公告)号：JPH08147611A
公开(公告)日：1996-06-07
申请号：JP29108594
申请日：1994-11-25
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , SHIROISHI YOSHIHIRO , TSUCHIYA REIJIROU , AKAGI KYO , HAMAGUCHI KATSUHIKO , KAWABE TAKASHI , SAITO ATSUSHI , WAKABAYASHI KOICHIRO
IPC分类号： G11B5/012 , G11B5/035 , G11B5/09 , G11B5/48 , G11B5/49 , G11B5/55 , G11B5/596 , G11B20/10
摘要： PURPOSE: To enhance a recording density by a method wherein a high-speed digital signal is converted into a plurality of low-speed digital signal sequences by means of a recording circuit and the respective low-speed digital signal series are recorded simultaneously in series by means of a plurality of recording heads. CONSTITUTION: Parallel recording tracks 1, 2 are treated as if they were one track. In the tracks 1, 2, phases are shifted in such a way that their magnetization inversion positions are not overlapped. A guard band is formed between the tracks 1, 2 and next tracks 1, 2. A high-speed digital signal 4 is input to a parallel-signal processing means 6 together with a high-speed clock signal 5, and it is separated into shift registers 8-1, 8-2 in units of prescribed bits by means of a switching circuit 7. Then, the signal 5 is read out by a 1/2 frequency-divided clock signal C2 and an inverted clock C3 so as to become low-speed digital signals D1, D2. Then, the signal D1 is recorded in a track 1 by means of a magnetic head 12a, and a signal D3 which has delayed the signal D2 by a delay circuit 11 is recorded in a track 2 by means of a magnetic head 12b.

35. 发明专利

JPH088788A DECISION FEEDBACK EQUALIZER 失效
公开(公告)号：JPH088788A
公开(公告)日：1996-01-12
申请号：JP14140794
申请日：1994-06-23
申请人： HITACHI LTD
发明人： SAKURAI WATARU , SAWAGUCHI HIDEKI , SATO NAOKI , UMEMOTO MASUO
IPC分类号： G11B20/10 , H04B1/10 , H04B3/06 , H04B3/08 , H04L25/03
摘要： PURPOSE:To obtain a low cost and high speed decision feedback equalizer by providing data holding means which are the same number as the number of the value that a decision result is possible to take and a selection means defining the decision result as a control signal. CONSTITUTION:The outputs 7 of a decision means 6 are inputted in a feedback signal candidate generation means 8 and a selection means 14. The selection means 14 defines the outputs of the decision means 6 as selection control signals, selects either one of the feedback signals 13a and 13b held in data holding means 15a and 15b by depending on whether the selection control signals are '0' or '1', and outputs the signal as a feedback signal 9 to a subtraction means 4. The generation means 8 repeats an operation that the signal 13a when the next decision result is '0' and the signal 13b when the next decision result is '1' are generated, when the decision result is obtained. Therefore, by composing the data holding means 15a and 15b and the selection means 14 by high speed elements, the operations can be made at high speed and the speed-up becomes possible at low cost.

36. 发明专利

JPH0778421A REPRODUCING SYSTEM OF DIGITAL SIGNAL AND RECORDING AND REPRODUCING DEVICE FOR DIGITAL SIGNAL 失效
公开(公告)号：JPH0778421A
公开(公告)日：1995-03-20
申请号：JP22195093
申请日：1993-09-07
申请人： HITACHI LTD
发明人： SETOYAMA TORU , UMEMOTO MASUO , ISHII HIROTAKE
IPC分类号： G11B20/14 , H04L25/497
摘要： PURPOSE:To apply the decoding circuit of interleaved NRZI to a magnetic recording and reproducing system while maintaining the transmission characteristics of modulation code such as 8-14 modulation code. CONSTITUTION:The reproducing signal inputted in an input terminal 1 for reproducing signal is inputted in a (1+D) processing circuit 2, and consecutive two bits are added to the signal. Then the signal is inputted in an identification circuit 3, processed with a usual interleaved NRZI decoding and outputted. From this signal, one consecutive for two bits is detected by a detecting circuit 4, and the polarities of the output signal are inverted with this detecting timing. This output signal is the same as an 8-14 conversion signal or the signal with the polarities inverted of the 8-14 conversion code; and when the signal is inputted in an 8-14 conversion demodulator circuit 5, the signal is normally demodulated.

37. 发明专利

JPH06231545A METHOD AND APPARATUS FOR RECORDING AND ENCODING DIGITAL SIGNAL 失效
公开(公告)号：JPH06231545A
公开(公告)日：1994-08-19
申请号：JP1523393
申请日：1993-02-02
申请人： HITACHI LTD
发明人： ISHII HIROTAKE , UMEMOTO MASUO , SAWAMURA HIDEHIKO
IPC分类号： G11B20/14 , H03M7/14 , H04N5/92
摘要： PURPOSE:To reduce the DC component of random data signals. CONSTITUTION:An m-bit data word delayed by one clock from a data word clock is obtained by a delay element 1, a data word delayed by two clocks is obtained by a delay element 2, and a data word m3 which is not delayed, a data word m2 which is delayed by one clock, a data word m1 which is delayed by two clocks and an already converted code word n0 are input to a converter 3. The converter 3 outputs a code word n1 for the m1 and a code word n2 for the m2. The n1, n2 of code words are converted to serial data of 1 bit at each 1/2-fold data word clock of an output of a 1/2 frequency divider 4 by using a clock having a frequency of n-fold of data word clock by a P/S converter 5 to obtain record data.

38. 发明专利

JPH0660552A METHOD FOR RECORDING AND ENCODING DIGITAL SIGNAL 失效
公开(公告)号：JPH0660552A
公开(公告)日：1994-03-04
申请号：JP21395892
申请日：1992-08-11
申请人： HITACHI LTD
发明人： ISHII HIROTAKE , UMEMOTO MASUO , SAWAMURA HIDEHIKO
IPC分类号： G11B20/12 , G11B20/14
摘要： PURPOSE:To reduce the maximum value (k) in a continuous number while making the minimum value of the continuous number of the same bit in a code group (d)-bits or above. CONSTITUTION:A cord word is divided into a part where the same bit continues in a leading part, the part where the same bit continues in a final part and an intermediate part except the two parts, and the continuous number of the same bit in the leading part and the final part are taken as k1, k2. When the maximum values of k1, k2 in total code words are taken as k1 max and k2 max, the code word is used where k1 max+k2 mak=k is satisfied together with the condition the continuous number of the same bits in the intermediate part of the code word except the parts of k1 bit and k2 bit of the code word is equal to or more then (d)-bits and equal to or less than (k)-bits. At this time, the code word where the continuous number of the same bits in the intermediate part is more than k/2-bits and equal to or less than (k)-bits is included in all code words, and plural code words are allocated for a data word, and a code word group in a present data word, the code word immediately before and a code word group in the data word immediately after is referred to, and the present data word is converted into the code word.

39. 发明专利

JPH0452546B2 失效
公开(公告)号：JPH0452546B2
公开(公告)日：1992-08-24
申请号：JP3641482
申请日：1982-03-10
申请人： HITACHI LTD
发明人： TANAKA SEIJI , UMEMOTO MASUO , TAKAHASHI KENJI , NAGAHARA SHUSAKU , MITA SEIICHI
IPC分类号： H04N5/93 , G11B20/06 , H04N5/922

40. 发明专利

JPH0423274A CONCURRENT RECORDING AND REPRODUCING DIGITAL VTR 失效
公开(公告)号：JPH0423274A
公开(公告)日：1992-01-27
申请号：JP12670790
申请日：1990-05-18
申请人： HITACHI LTD
发明人： UMEMOTO MASUO
IPC分类号： G11B5/09 , G11B20/18
摘要： PURPOSE:To reduce the number of channels of a rotary transformer by supplying the rotary transformer with a regenerative signal of each reproducing head under a changeover of a single of plural heads in synchronization with a rotary drum at the time of recording. CONSTITUTION:At the time of recording, a signal from a reproducing head 8 is amplified by a regenerative amplifier 9, and the signal of each individual head is supplied in turn by a switch circuit 10 to one channel of the rotary transformer 4. Moreover, on the output side of the rotary transformer 4, the regenerative signal received in turn is distributed by a switch circuit 11 to a channel corresponding to the reproducing head concerned, and is distributed by a switch circuit 12 to an equivalent circuit 13 to be restored to the original digital signal. Then, a spot where a code error is generated is detected by an error correction/modification circuit 14 to display a flag for showing the spot of generating the code error together with a recording picture data on a monitor. By this constitution, the number of channels of the rotary transformer 4 is reduced without deteriorating the concurrent recording and reproducing function as much as possible.

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