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31. 发明专利

JPH0651984A MICROPROCESSOR 失效
公开(公告)号：JPH0651984A
公开(公告)日：1994-02-25
申请号：JP12262293
申请日：1993-05-25
申请人： HITACHI LTD
发明人： YAMAMOTO MITSUTAKE , ARAKAWA FUMIO , NARITA SUSUMU
IPC分类号： G06F9/318 , G06F9/38
摘要： PURPOSE:To execute a high performance instruction at high speed by performing pipeline processing by providing a function to perform the parallel execution of plural instructions by using a pipeline, and a function to execute a single instruction. CONSTITUTION:A control part 11 is comprised of two instruction decoders 12, 13, a common micro ROM 14 in which a microinstruction group in accordance with a microinstruction supplied front a main memory device 2 is stored, selectors 16, 17 which select either of control signals outputted from the micro ROW 14 and the instruction decoders 12, 13 a selector control part 15 which forms the control signals st and vs of the selectors 16, 17, and buffers 18, 19 which hold the control signals from the instruction decoders 12, 13 or the micro ROM 14. The single instruction that can be executed in one cycle is parallel- executed by using plural pipelines independently, and also, the high performance instruction which requires a large amount of data processing and complicated processing can be executed by using the plural pipelines simultaneously.

32. 发明专利

JPH05251561A 失效
公开(公告)号：JPH05251561A
公开(公告)日：1993-09-28
申请号：JP4823992
申请日：1992-03-05
申请人： HITACHI LTD
发明人： UCHIYAMA KUNIO , AOKI HIROKAZU , KUDO IKUO , NARITA SUSUMU , ARAKAWA FUMIO
IPC分类号： H01L21/82 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To optimize a chip area and a delay time and minimize the man-hours related to layout in a semiconductor integrated circuit using a multilayered metal wiring technology by which a regular-structure block and a random block are integrated on one chip. CONSTITUTION:The most significant metal wiring layer is used for a bus wiring 127 to 132 in the inner part of an operating block 151 which is a regular- structure block. An intermediate metal wiring layer is used for a control signal 111 to 118. A control block 150, which is a random block, consists of an n- column standard cell 100. The least significant and the most significant metal wiring layer are used for a parallel wiring to the standard cell column which is a wiring between the standard cells and between the standard cell and the regular-structure block. The intermediate wiring layer is used for the wiring of a vertical direction. Thereby, a chip area and a delay time may be minimized and furthermore the man-hours of layout may be minimized.

33. 发明专利

JPH05241833A 失效
公开(公告)号：JPH05241833A
公开(公告)日：1993-09-21
申请号：JP4439392
申请日：1992-03-02
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： NARITA SUSUMU , ARAKAWA FUMIO , UCHIYAMA KUNIO , KAWASAKI IKUYA , MATSUI SHIGESUMI , HASHIMOTO KOJI
IPC分类号： G06F9/38
摘要： PURPOSE:To easily attain the program debug of the user of a microprocessor in which the simultaneously parallel and parallel execution of plural commands/ can be attained. CONSTITUTION:The operating mode of the simultaneous parallel and parallel execution is switched to the operating mode of a scalar system (the successive decode and successive execution of the plural commands) in the microprocessor. The setting of the mode is operated by setting a bit DB for a mode setting in a control register 118 in the microprocessor. The successive execution mode of the plural commands can be set in the microprocessor, so that the user can easily understand the operation of the microprocessor at the time of the debug of the program, and the debug efficiency of the program can be improved.

34. 发明专利

JPH04127250A MICROPROCESSOR CONTAINING BUS PARITY CONTROL MECHANISM 失效
公开(公告)号：JPH04127250A
公开(公告)日：1992-04-28
申请号：JP24712190
申请日：1990-09-19
申请人： HITACHI LTD
发明人： UCHIYAMA KUNIO , OKADA TETSUHIKO , NARITA SUSUMU , ARAKAWA FUMIO
IPC分类号： G06F11/10 , G06F11/30 , G06F12/16
摘要： PURPOSE:To construct a system having the high flexibility and reliability with least hardware quantity by providing a built-in parity check circuit and reporting an error to an instruction execution control part of a microprocessor via a signal line set on the same chip if the error is decided from the parity check result. CONSTITUTION:When the data are read out of a microprocessor 1, a parity circuit 11 performs a parity check operation. Then an OR is secured between the parity check output and the parity valid bit of a memory area control table 10 that is read out in parallel to the reading operation of the data on the microprocessor 1. This OR is inputted to an exception processing circuit 5. Therefore the parity is checked when the data are read out of an area added with the parity. An error if detected is immediately reported to the circuit 5. Meanwhile the bus parity error detection result is suppressed when the data are read out an area where no parity is added. Thus it is possible to construct a system having the high flexibility and reliability with the least hardware quantity.

35. 发明专利

JPH04127074A LOGIC CIRCUIT AND DRIVE LOGIC CIRCUIT 失效
公开(公告)号：JPH04127074A
公开(公告)日：1992-04-28
申请号：JP24713690
申请日：1990-09-19
申请人： HITACHI LTD
发明人： OKADA TETSUHIKO , UCHIYAMA KUNIO , NARITA SUSUMU , ARAKAWA FUMIO , MATSUMOTO YOSHIHIRO
IPC分类号： G01R31/28
摘要： PURPOSE:To achieve higher reliability of an LSI by adding a signal line for testing which generates an input signal adapted to operate one logic circuit alone and a logic to enable the testing of logic circuits built redundant. CONSTITUTION:Besides a control signal 11, a PMOS test signal 21 for generating drive signals 12 and 13 and an NMOS test signal 22 are added to a drive element 20 with a testing function to generate a drive signal of complement type pass transistors 100-103. Normally, the connection and separation between input data lines 110-113 and output data lines 120-123 are controlled by the signal 11. When an NMOS is tested, with the signal 22 to L, the drive signal 13 always goes to H and a PMOS is always cut. Under such a condition, when the signal 11 is controlled and values of the output lines 120-123 are observed varying values of the input lines 110-113, a trouble of the NMOS can be inspected. Likewise, when the signal 21 is turned to L, the NMOS alone is cut and the PMOS can be inspected.

36. 发明专利

JPH02259839A DATA PROCESSOR 失效
公开(公告)号：JPH02259839A
公开(公告)日：1990-10-22
申请号：JP7822589
申请日：1989-03-31
申请人： HITACHI LTD
发明人： HANAWA MAKOTO , NARITA SUSUMU , OKADA TETSUHIKO
IPC分类号： G06F9/34 , G06F9/46 , G06F9/48
摘要： PURPOSE:To execute an exception processing without generating contradiction even when one instruction is executed by dividing into two steps by setting the address of the next step on a program counter when no execution result of the step is stored in an accumulator. CONSTITUTION:When a microprocessor 100 executes one instruction by dividing into plural steps, a control circuit 140 judges whether or not the result of the execution of an instruction step obtained from an instruction decoder 130 is stored in the accumulator AccA 161 for address computation or the accumulator AccD 171 for data. When no result is stored, the address of decode half word of the next step is set from an instruction address register IAR 124 on the program counter PC 159. Thereby, it is possible to easily restart the instruction by using the address held at the program counter after completing the exception processing even when an exceptional event occurs on the middle way of the execution of the instruction.

37. 发明专利

JPS6390097A MICROPROCESSOR BUILT-IN DYNAMIC MEMORY 失效
公开(公告)号：JPS6390097A
公开(公告)日：1988-04-20
申请号：JP23459386
申请日：1986-10-03
申请人： HITACHI LTD
发明人： IWASAKI KAZUHIKO , HANAWA MAKOTO , TONOMURA MOTONOBU , NARITA SUSUMU
IPC分类号： G06F9/30 , G11C11/34 , G11C11/406
摘要： PURPOSE:To fix the execution time of a microinstruction by refreshing an on-chip dynamic memory by the microinstruction. CONSTITUTION:The microinstruction read out from a ROM 5 is latched by a register 7 to control an execution part 3 through a line 11 and control a dynamic memory part 4 through lines 12-16 respectively. A microprogram counter 9 indicate the address of the read microinstruction and applies the address to the ROM 5 and an incrementer 10. A multiplexer 8 sends either one of the output of the incrementer 10 and the output of the line 16 to the counter 9. At the time of the switching, the 'H' level of the line 12 indicates a normal microinstruction and the 'L' level indicates a branch microinstruction. Thereby, the incrementer 10 is selected when the line 12 is 'H', and in case of 'L', the line 16 is selected.

38. 发明专利

JPS6367658A PARALLEL ACCESS MECHANISM FOR ON-CHIP MEMORY 失效
公开(公告)号：JPS6367658A
公开(公告)日：1988-03-26
申请号：JP21156186
申请日：1986-09-10
申请人： HITACHI LTD
发明人： NARITA SUSUMU
IPC分类号： G06F12/02 , G06F12/00 , G06F12/06 , G06F13/18 , G11C7/00
摘要： PURPOSE:To reduce the processor load and to increase the data transfer speed by using a processor different from a primary processor and more approximate to a memory to produce addresses when a large quantity of data containing continuous addresses are transferred. CONSTITUTION:The memories MB0-MB2 divided into banks are connected with address generating circuits AG0 and AG1 via a network ANW exclusive for address lines. The number of address generating circuits are set equal to the number of data processing parts where data are transferred with those memories MB0-MB3 and connected to the ANW independently of each other. Thus all address generating parts and the ANW are controlled by a single control part CONT. Thus plural address generating parts are provided in the vicinity of the memories and controlled collectively. Thus it is possible to give parallel accesses to the memories with good timing. In addition, the divided memories can be used as a single shared memory by means of the network ANW.

39. 发明专利

JP2007259463A Low power processor 有权
标题翻译：低功率处理器
公开(公告)号：JP2007259463A
公开(公告)日：2007-10-04
申请号：JP2007101243
申请日：2007-04-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TOTSUKA YONETARO , ISHIBASHI KOICHIRO , MIZUNO HIROYUKI , NISHII OSAMU , UCHIYAMA KUNIO , SHIMURA TAKANORI , SEKINE ASAKO , KATSUKI YOICHI , NARITA SUSUMU
IPC分类号： H03K19/00 , G06F15/78 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K19/094
CPC分类号： Y02D10/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit managing both a high speed and low power consumption. SOLUTION: The low power processor has a logic circuit 902 and a substrate bias control circuit 903. The logic circuit is controlled so as not to change inputs of the logic circuit after switched to a low power mode in response to the execution of an instruction. After the circuit is switched to a high-speed mode in response to an interruption, the circuit starts operation after a substrate bias voltage applied to an MOS transistor of the logic circuit has been stabilized to a predetermined level. COPYRIGHT: (C)2008,JPO&INPIT

40. 发明专利

JP2002063149A DATA PROCESSING SYSTEM 失效
公开(公告)号：JP2002063149A
公开(公告)日：2002-02-28
申请号：JP2001156250
申请日：2001-05-25
申请人： HITACHI LTD
发明人： MATSUI SHIGESUMI , KAWASAKI IKUYA , NARITA SUSUMU , NEMOTO MASATO
IPC分类号： G06F13/12 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a data processing system which is satisfactory in handleability. SOLUTION: A data processor is constituted to be connectable to a memory card or a PC card including an I/O card; a first PC card connector is constituted to be connectable to the PC card; and the external bus is divided into plural areas fixedly assigned to a ROM, a DRAM, and the PC card, and connected to the data processor, the ROM, the DRAM, and the first PC card connector. The data processor performs access to the external bus, based on a physical address in an address space. The data processor is provided with a central processing unit, which outputs an internal logical address and a memory managing unit connected to the central processing unit, which outputs the physical address to the external bus, based on the internal logical address.

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