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31. 发明专利

JPS58142674A DATA PROCESSING DEVICE FOR FACSIMILE 失效
公开(公告)号：JPS58142674A
公开(公告)日：1983-08-24
申请号：JP2444282
申请日：1982-02-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YAJIMA YOSHIYUKI , HARA HIDEO , TORII SHIYUUICHI
IPC分类号： H04N1/401 , H04N1/40 , H04N1/403
摘要： PURPOSE:To use a low-speed A/D conversion circuit, by making writing speed in storing data on shading distortion in a memory slower than memory reading speed. CONSTITUTION:Shading distorsion for determining a slice level, i.e, the reference voltae of a comparator 7 is read and stored in a memory 5. In this case, a circuit of low-speed system is used as an A/D conversion circuit 3, a sampling signal phis of 100KHz which is slower than a clock signal phic of 1MHz that drives an image sensor 1 is supplied from a timing generation circuit 4 to the circuit 3. The same place of an original is scanned repeatedly by a sensor 1 and the sampling position is shifted. By this way, the same data as in the case where scanning speed of the sensor 1 is A/D-converted at the same speed can be stored in the memory 5.

32. 发明专利

JPS5648698A SOUND GENERATION CIRCUIT 失效
公开(公告)号：JPS5648698A
公开(公告)日：1981-05-01
申请号：JP12413879
申请日：1979-09-28
申请人： HITACHI LTD
发明人： HARA HIDEO , TORII SHIYUUICHI , NISHIHARA TATSUYA
IPC分类号： H04R3/00

33. 发明专利

JPS5648696A SOUND GENERATION CIRCUIT 失效
公开(公告)号：JPS5648696A
公开(公告)日：1981-05-01
申请号：JP12412879
申请日：1979-09-28
申请人： HITACHI LTD
发明人： TORII SHIYUUICHI , HARA HIDEO , NISHIHARA TATSUYA
IPC分类号： H04R3/00

34. 发明专利

JPS5648694A SOUND GENERATION CIRCUIT 失效
公开(公告)号：JPS5648694A
公开(公告)日：1981-05-01
申请号：JP12410879
申请日：1979-09-28
申请人： HITACHI LTD
发明人： TORII SHIYUUICHI , HARA HIDEO , NISHIHARA TATSUYA
IPC分类号： H03B28/00 , H03K4/02 , H04R3/00

35. 发明专利

JPS5635256A ELECTRONIC DESK COMPUTER 失效
公开(公告)号：JPS5635256A
公开(公告)日：1981-04-07
申请号：JP10913379
申请日：1979-08-29
申请人： HITACHI LTD
发明人： HARA HIDEO
IPC分类号： G06F15/02 , G06F3/14 , G06F3/147
摘要： PURPOSE:To eliminate a conversion for reading of the display, by displaying an integer-fold figure of 3 or 4 or the character, the voice and others corresponding to these figures at the exponent part. CONSTITUTION:In case the result of operation is displayed through the mantissa part A composed of e.g. 8 digits and the exponent part A composed of 2 digits each, the display at the part B is limited to an integer-fold value of e.g. 3. And the segment displaying the decimal point is provided to each digit, and the digit of the decimal point is decided according to the display at the part A. In the case of display of e.g. 1,2345678X10 , 03 is displayed at the part B along 123,45678 is displayed at the part A respectively. Also an integer-fold figure of 3 is set to the part B, and thus the display is possible with the character corresponding to the figure. In addition, the compound voice circuit is provided to carry out the display via the voice. And in case a calculation is carried out in the Japanese yen, the exponent part can be displayed with an integer-fold figure of 4.

36. 发明专利

JPS53105350A INITIALIZING METHOD 失效
公开(公告)号：JPS53105350A
公开(公告)日：1978-09-13
申请号：JP1923577
申请日：1977-02-25
申请人： HITACHI LTD
发明人： HARA HIDEO
IPC分类号： G01R31/28 , G06F1/04 , G06F1/24 , H03K3/356 , H03K17/22
摘要： PURPOSE:To enable initializing without increasing the number of IC pins, by superimposing the first and second clock pulses controlling FF at initialize.

37. 发明专利

JPH0855483A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0855483A
公开(公告)日：1996-02-27
申请号：JP21317894
申请日：1994-08-15
申请人： HITACHI LTD
发明人： KATO KEI , IWAMURA MASAHIRO , OGUCHI SATOSHI , HARA HIDEO
IPC分类号： G11C11/419 , G11C11/409
摘要： PURPOSE:To maintain low power consumption of a device and to increase operation speed by controlling a driving current in each mode of a normal operation state, a standby state and a stop state of a differential circuit. CONSTITUTION:In a normal operation mode of a memory with a logical function and in a selecting state in a read-mode of a corresponding memory module, a driving current value supplied to differential circuits DC1, 2 through an internal node n1 is made large by large conductance of MOSFET NE, NF. Also, in a normal operation mode and in a non-selection state of a corresponding memory module or in a write-mode and in a selection mode, conductance of FETNC is restricted, and a supplied driving current value of the circuits DC1, 2 is made small. When a memory with a logical function is made a standby mode, an internal control signal RMO and a standby signal STB both are made a low level, a driving path of a sense amplifier consisting of the circuits DC1, 2 is cut off and a current is not made to flow. Thereby, low power consumption of the memory module and the memory are maintained and operation speed is increased.

38. 发明专利

JPH07135462A SEMICONDUCTOR LOGIC CIRCUIT AND ITS OUTPUT COUPLING CIRCUIT 失效
公开(公告)号：JPH07135462A
公开(公告)日：1995-05-23
申请号：JP27059993
申请日：1993-10-28
申请人： HITACHI LTD
发明人： IWAMURA MASAHIRO , HOSONO TOMOHISA , HARA HIDEO
IPC分类号： H01L21/8234 , H01L27/088 , H03K17/08 , H03K19/003 , H03K19/0175
摘要： PURPOSE:To prevent the increase in power consumption and the destruction of elements at the coupling of plural circuits by connecting a Schottky barrier diode blocking a reverse current between a drain of a PMOS transistor(TR) and an output terminal. CONSTITUTION:A Schottky barrier diode 2 is connected between a drain D of a PMOS transistor(TR) and an output terminal 7 in the semiconductor conductor logic circuit in a direction of blocking a current flowing to the TR 1. Thus, even when a voltage higher than a voltage V at a power terminal 6 is applied to the output terminal 7 due to some cause, the high voltage is effectively blocked by the reverse direction transmission characteristic of the diode 2. Thus, no high voltage is sent to the TR 1 and an undesired TR current and diode current flows based on the high voltage. Thus, even when output terminals of the 1st and 2nd semiconductor logic circuits different from the voltage are connected in common to the coupling bus, the increase in the power consumption of the circuit in the stop state and operating state is suppressed and the destruction in the pause state circuit is prevented in advance.

39. 发明专利

JPH0578963B2 失效
公开(公告)号：JPH0578963B2
公开(公告)日：1993-10-29
申请号：JP24061484
申请日：1984-11-16
申请人： HITACHI LTD
发明人： HARA HIDEO
IPC分类号： H03B28/00 , H03L3/00 , H04M1/50

40. 发明专利

JPS616470B2 JPS616470B2 - 失效
公开(公告)号：JPS616470B2
公开(公告)日：1986-02-26
申请号：JP14420678
申请日：1978-11-24
申请人： Hitachi Ltd
发明人： HARA HIDEO
IPC分类号： G11C11/41 , G11C5/14
CPC分类号： G11C5/14

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