专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07605447B2 Highly manufacturable SRAM cells in substrates with hybrid crystal orientation 有权
标题翻译：具有混合晶体取向的基板中的高度可制造的SRAM单元
公开(公告)号：US07605447B2
公开(公告)日：2009-10-20
申请号：US11162780
申请日：2005-09-22
申请人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L29/06 , H01L29/04 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

32. 发明申请

US20090091037A1 Methods for Fabricating Contacts to Pillar Structures in Integrated Circuits 有权
标题翻译：在集成电路中制造与柱结构的接触的方法
公开(公告)号：US20090091037A1
公开(公告)日：2009-04-09
申请号：US11866455
申请日：2007-10-03
申请人： Solomon Assefa , Gregory Costrini , Christopher Vincent Jahnes , Michael J. Rooks , Jonathan Zanhong Sun
发明人： Solomon Assefa , Gregory Costrini , Christopher Vincent Jahnes , Michael J. Rooks , Jonathan Zanhong Sun
IPC分类号： H01L21/768 , H01L23/52
CPC分类号： H01L43/12
摘要： A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.
摘要翻译：在集成电路中形成由垂直接触件接触的柱结构。硬掩模被形成并用于对柱结构的至少一部分进行图案化。硬掩模包含碳。随后，去除硬掩模。然后将导电材料沉积在先前由硬掩模占据的区域中以形成垂直接触。硬掩模可以例如包括类金刚石碳。柱结构可以具有小于约100纳米的宽度或直径。

33. 发明申请

US20090090974A1 DUAL STRESS LINER STRUCTURE HAVING SUBSTANTIALLY PLANAR INTERFACE BETWEEN LINERS AND RELATED METHOD 审中-公开
标题翻译：具有线性和相关方法之间的主要平面界面的双应力衬里结构
公开(公告)号：US20090090974A1
公开(公告)日：2009-04-09
申请号：US11868567
申请日：2007-10-08
申请人： Gregory Costrini , David M. Fried , Werner A. Rausch , Christopher D. Sheraw
发明人： Gregory Costrini , David M. Fried , Werner A. Rausch , Christopher D. Sheraw
IPC分类号： H01L27/092 , H01L21/311
CPC分类号： H01L21/823807 , H01L21/31111 , H01L29/7843
摘要： A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile stress liner over an NFET, the NFET including a PFET adjacent thereto; and a compressive stress liner over the PFET, wherein an upper surface of the compressive stress liner is substantially planar with an upper surface of the tensile stress liner at an interface therebetween.
摘要翻译：公开了一种在衬垫之间具有基本平坦的界面的双重应力衬垫结构和相关方法。在一个实施例中，双应力衬垫结构可以包括在NFET上的拉伸应力衬垫，NFET包括与其相邻的PFET; 以及PFET上的压应力衬垫，其中所述压应力衬垫的上表面在其间的界面处与所述拉伸应力衬垫的上表面基本上是平面的。

34. 发明申请

US20080272398A1 CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING 有权
标题翻译：用于半导体器件的导电间隔件和形成方法
公开(公告)号：US20080272398A1
公开(公告)日：2008-11-06
申请号：US11848597
申请日：2007-08-31
申请人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
发明人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
IPC分类号： H01L29/00
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

35. 发明申请

US20080233743A1 Method and Structure for Self-Aligned Device Contacts 有权
标题翻译：自对准器件触点的方法和结构
公开(公告)号：US20080233743A1
公开(公告)日：2008-09-25
申请号：US12110465
申请日：2008-04-28
申请人： Gregory Costrini , David M. Fried
发明人： Gregory Costrini , David M. Fried
IPC分类号： H01L21/768
CPC分类号： H01L29/458 , H01L21/76829 , H01L21/76897 , H01L21/84 , H01L27/12 , H01L29/41733 , H01L29/665 , H01L29/6656 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.
摘要翻译：公开了在接触件的下部具有部分自对准接触的半导体结构的实施例，以减小电阻而不会影响器件的产量。另外，该结构可选地包含厚中间线（MOL）氮化物应力膜以增强载流子迁移率。形成结构的方法的实施例包括在接触的预期位置形成牺牲部分。该部分被图案化，使得其与栅电极自对准，并且仅占用用于将来接触的空间。一旦牺牲部分就位就可以沉积介电层（例如，任选的应力层，然后是层间电介质）。常规的接触光刻用于蚀刻通过介电层到牺牲部分的接触孔。然后选择性地去除牺牲部分以形成空腔，并且在空腔和接触孔中形成接触。

36. 发明申请

US20080166857A1 ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT 有权
标题翻译：氧化铝层和集成电路下面形成的导电路径
公开(公告)号：US20080166857A1
公开(公告)日：2008-07-10
申请号：US11621699
申请日：2007-01-10
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

37. 发明授权

US07374952B2 Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof 有权
标题翻译：图案化磁性存储单元的磁性堆叠的方法及其结构
公开(公告)号：US07374952B2
公开(公告)日：2008-05-20
申请号：US10870756
申请日：2004-06-17
申请人： Ihar Kasko , Sivananda K. Kanakasabapathy , Gregory Costrini
发明人： Ihar Kasko , Sivananda K. Kanakasabapathy , Gregory Costrini
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/228
摘要： Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is patterned using a hard mask, and a conformal insulating material is deposited over the patterned top magnetic material layer and hard mask. The conformal insulating material is anisotropically etched to remove the conformal insulating material over vertical sidewalls of at least the patterned top magnetic material layer and the hard mask. The remaining conformal insulating material comprises a sidewall spacer hard mask that is used as a mask to pattern the remaining material layers of the magnetic stack. The sidewall spacer hard mask may be left remaining in the magnetic memory cell structure.
摘要翻译：图案化磁性存储单元的磁性堆叠的方法及其结构。至少使用硬掩模对磁性堆叠的顶部磁性材料层进行构图，并且在图案化的顶部磁性材料层和硬掩模上沉积保形绝缘材料。各向异性蚀刻保形绝缘材料，以在至少图案化的顶部磁性材料层和硬掩模的垂直侧壁上去除保形绝缘材料。剩余的共形绝缘材料包括侧壁间隔物硬掩模，其用作掩模以对磁性堆叠的剩余材料层进行图案化。侧壁间隔物硬掩模可以留在磁存储单元结构中。

38. 发明申请

US20070063278A1 HIGHLY MANUFACTURABLE SRAM CELLS IN SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION 有权
标题翻译：具有混合晶体取向的衬底中的高度可制造的SRAM电池
公开(公告)号：US20070063278A1
公开(公告)日：2007-03-22
申请号：US11162780
申请日：2005-09-22
申请人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L27/12
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

39. 发明授权

US06187680B1 Method/structure for creating aluminum wirebound pad on copper BEOL 失效
标题翻译：用于在BEOL上生成铝线焊盘的方法/结构
公开(公告)号：US06187680B1
公开(公告)日：2001-02-13
申请号：US09167834
申请日：1998-10-07
申请人： Gregory Costrini , Ronald Dean Goldblatt , John Edward Heidenreich, III , Thomas Leddy McDevitt
发明人： Gregory Costrini , Ronald Dean Goldblatt , John Edward Heidenreich, III , Thomas Leddy McDevitt
IPC分类号： H01L2144
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/1191 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48799 , H01L2224/48824 , H01L2224/48847 , H01L2924/0001 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01043 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/29099 , H01L2224/05552 , H01L2924/00015
摘要： The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.
摘要翻译：本发明提供了一种用于制造集成电路（IC）结构的方法，该集成电路（IC）结构具有与嵌入在初始半导体晶片中的Cu布线电连通的Al接触。根据本发明的方法，在包含或不包含Cu布线的下部区域的IC结构的区域中形成Al触点。本发明还提供了一种通过使用引线键或受控塌陷芯片连接（C4）焊料将制造的结构与半导体封装材料互连的方法。

40. 发明授权

US5843800A Gettering of particles from an electro-negative plasma with insulating chuck 失效
公开(公告)号：US5843800A
公开(公告)日：1998-12-01
申请号：US711572
申请日：1996-09-10
申请人： John H. Keller , Gregory Costrini
发明人： John H. Keller , Gregory Costrini
IPC分类号： H01J37/32 , H05H1/00 , H01L21/00
CPC分类号： H01J37/32174 , H01J37/32082 , H01J37/32623 , H01J37/32706 , H01J37/32963
摘要： Apparatus controls a wafer potential in a plasma system when the plasma is off to keep the wafer slightly negative at all times in order to reduce and eliminate the collection of charged particles on the wafer. The apparatus allows the wafer bias to be reduced to a small negative voltage and then holds that voltage. This greatly reduces the net positive flux to the wafer. A diode and a programmed power supply hold a minimum negative voltage on the back of the wafer electrode when the plasma density is decaying to zero.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式