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31. 发明授权

US07718504B2 Semiconductor device having align key and method of fabricating the same 失效
标题翻译：具有对准键的半导体器件及其制造方法
公开(公告)号：US07718504B2
公开(公告)日：2010-05-18
申请号：US11535934
申请日：2006-09-27
申请人： Sang-Su Kim , In-Wook Cho , Myeong-Cheol Kim , Sung-Woo Lee , Jin-Hee Kim , Doo-Youl Lee , Sung-Ho Kim
发明人： Sang-Su Kim , In-Wook Cho , Myeong-Cheol Kim , Sung-Woo Lee , Jin-Hee Kim , Doo-Youl Lee , Sung-Ho Kim
IPC分类号： H01L21/76 , H01L21/46
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.
摘要翻译：公开了具有对准键的半导体器件及其制造方法。半导体器件包括具有单元区域和对准键区域的半导体衬底。限定电池有源区的隔离层设置在半导体衬底的单元区域中。电池电荷存储层图案跨越电池有源区域设置。对准电荷存储层图案设置在半导体衬底的对准键区域中。在对准电荷存储层图案中自对准的对准沟槽形成在半导体衬底的对准键区域中。

32. 发明申请

US20080108197A1 Method of fabricating non-volatile flash memory device having at least two different channel concentrations 失效
标题翻译：制造具有至少两个不同通道浓度的非易失性闪速存储器件的方法
公开(公告)号：US20080108197A1
公开(公告)日：2008-05-08
申请号：US12007097
申请日：2008-01-07
申请人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
发明人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
IPC分类号： H01L21/334
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.
摘要翻译：在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案，电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及覆盖屏蔽层图案的栅电极和栅极绝缘层。

33. 发明授权

US07320920B2 Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same 失效
标题翻译：具有至少两种不同通道浓度的非挥发性闪存器件及其制造方法
公开(公告)号：US07320920B2
公开(公告)日：2008-01-22
申请号：US11097281
申请日：2005-04-04
申请人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
发明人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
IPC分类号： H01L21/334
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.
摘要翻译：在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案，电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及覆盖屏蔽层图案的栅电极和栅极绝缘层。

34. 发明申请

US20060011965A1 Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same 失效
标题翻译：具有至少两种不同通道浓度的非挥发性闪存器件及其制造方法
公开(公告)号：US20060011965A1
公开(公告)日：2006-01-19
申请号：US11097281
申请日：2005-04-04
申请人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
发明人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.
摘要翻译：在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案，电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及覆盖屏蔽层图案的栅电极和栅极绝缘层。

35. 发明申请

US20050104229A1 Semiconductor device having align key and method of fabricating the same 失效
标题翻译：具有对准键的半导体器件及其制造方法
公开(公告)号：US20050104229A1
公开(公告)日：2005-05-19
申请号：US10982685
申请日：2004-11-04
申请人： Sang-Su Kim , In-Wook Cho , Myeong-Cheol Kim , Sung-Woo Lee , Jin-Hee Kim , Doo-Youl Lee , Sung-Ho Kim
发明人： Sang-Su Kim , In-Wook Cho , Myeong-Cheol Kim , Sung-Woo Lee , Jin-Hee Kim , Doo-Youl Lee , Sung-Ho Kim
IPC分类号： H01L21/027 , H01L21/8247 , H01L23/544 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.
摘要翻译：公开了具有对准键的半导体器件及其制造方法。半导体器件包括具有单元区域和对准键区域的半导体衬底。限定电池有源区的隔离层设置在半导体衬底的单元区域中。电池电荷存储层图案跨越电池有源区域设置。对准电荷存储层图案设置在半导体衬底的对准键区域中。在对准电荷存储层图案中自对准的对准沟槽形成在半导体衬底的对准键区域中。

36. 发明申请

US20160307927A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160307927A1
公开(公告)日：2016-10-20
申请号：US14993212
申请日：2016-01-12
申请人： Jung-Han Lee , Jae-Hwan Lee , Sang-Su Kim , Hwan-Wook Choi , Tae-Jong Lee , Seung-Mo Ha
发明人： Jung-Han Lee , Jae-Hwan Lee , Sang-Su Kim , Hwan-Wook Choi , Tae-Jong Lee , Seung-Mo Ha
IPC分类号： H01L27/12 , H01L29/06 , H01L27/088
CPC分类号： H01L29/0657 , H01L21/823431 , H01L21/823468 , H01L27/0886
摘要： A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
摘要翻译：半导体器件包括由衬底上的隔离层限定的多个有源散热片，活性散热片上的栅极结构和隔离层，以及覆盖栅极结构的侧壁的栅极间隔结构。栅极结构的侧壁分别包括具有第一，第二和第三斜率的第一，第二和第三区域。第二斜坡从底部向第二区域的顶部增加。第二斜坡在第二区域的底部具有小于第一斜坡的值。第三斜率大于第二斜率。

37. 发明申请

US20150279995A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150279995A1
公开(公告)日：2015-10-01
申请号：US14669082
申请日：2015-03-26
申请人： Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
发明人： Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/823431 , H01L21/823437 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
摘要翻译：形成半导体器件的方法可以包括形成在衬底上沿第一方向延伸的鳍式有源图案，鳍型有源图案包括在衬底上的下图案和下图案上的上图案。场绝缘层形成在衬底上，翅片型有源图案的侧壁和远离衬底的部分上部图案远离场绝缘层的顶表面。形成与翅片型有源图案相交并且沿与第一方向不同的第二方向延伸的伪栅极图案。所述方法包括在伪栅极图案的侧壁上形成虚拟栅极间隔物，在虚拟栅极图案的两侧上形成鳍状有源图案中的凹槽，并在虚拟栅极图案的两侧形成源区和漏极区。

38. 发明申请

US20050067651A1 Nonvolatile memory cell employing a plurality of dielectric nanoclusters and method of fabricating the same 审中-公开
标题翻译：采用多个介电纳米簇的非易失性存储单元及其制造方法
公开(公告)号：US20050067651A1
公开(公告)日：2005-03-31
申请号：US10944382
申请日：2004-09-16
申请人： Ki-Chul Kim , Byou-Ree Lim , Sang-Su Kim , Byoung-Jin Lee , In-Wook Cho
发明人： Ki-Chul Kim , Byou-Ree Lim , Sang-Su Kim , Byoung-Jin Lee , In-Wook Cho
IPC分类号： H01L27/115 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/792 , H01L29/76
CPC分类号： H01L29/792 , B82Y10/00 , H01L29/40114 , H01L29/40117 , H01L29/42332 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833
摘要： A nonvolatile memory cell employing a plurality of dielectric nanoclusters and a method of fabricating the same are disclosed. In one embodiment, the nonvolatile memory cell comprises a semiconductor substrate having a channel region. A control gate is disposed above the channel region. A control gate dielectric layer is disposed between the channel region and the control gate. A plurality of dielectric nanoclusters are disposed between the channel region and the control gate dielectric layer. Each nanocluster may be separated from adjacent nanoclusters by the control gate dielectric layer. A tunnel oxide layer is disposed between the plurality of dielectric nanoclusters and the channel region. Further, a source and a drain are formed in the semiconductor substrate.
摘要翻译：公开了一种采用多个电介质纳米簇的非易失性存储单元及其制造方法。在一个实施例中，非易失性存储单元包括具有沟道区的半导体衬底。控制门设置在通道区域的上方。控制栅介质层设置在沟道区和控制栅之间。多个介电纳米团簇设置在沟道区和控制栅介质层之间。每个纳米团簇可以通过控制栅极介电层与相邻的纳米团簇分离。隧道氧化层设置在多个介电纳米簇与沟道区之间。此外，在半导体衬底中形成源极和漏极。

39. 发明授权

US09194035B2 Non-adhesive sputtering structure including a sputtering target and backing plate 有权
标题翻译：包括溅射靶和背板的非粘性溅射结构
公开(公告)号：US09194035B2
公开(公告)日：2015-11-24
申请号：US13537867
申请日：2012-06-29
申请人： Kyung Il Park , Keun-Ik Jeon , Sang-Su Kim , Youn-Yong Lee
发明人： Kyung Il Park , Keun-Ik Jeon , Sang-Su Kim , Youn-Yong Lee
IPC分类号： C23C14/24 , C23C14/34 , H01J37/32 , H01J37/34
CPC分类号： C23C14/3407 , H01J37/32522 , H01J37/3435 , H01J37/3497 , Y10T29/49947
摘要： A non-adhesive sputtering structure includes a sputtering target having a plate shape; and a backing plate having a plate shape. The backing plate faces the sputtering target, and facing surfaces of the sputtering target and the backing plate are in contact with each other. The backing plate includes a body having a longitudinal axis; and a cooling member through which a cooling material flows in a longitudinal direction of the body substantially parallel to the longitudinal axis. The cooling material conducts heat generated from the sputtering target from sputtering to outside the backing plate. The non-adhesive sputtering structure further includes a plurality of non-adhesive fastening members which maintain the facing surfaces of the backing plate and the sputtering target in contact with each other. The non-adhesive fastening members are extended through a thickness of the backing plate and correspond to regions of the backing plate excluding the cooling member.
摘要翻译：非粘合溅射结构包括具有板形的溅射靶; 以及具有板形的背板。背板面对溅射靶，并且溅射靶和背板的相对表面彼此接触。背板包括具有纵向轴线的主体; 以及冷却构件，冷却材料通过所述冷却构件沿主体的纵向方向基本上平行于纵向轴线流动。冷却材料将溅射靶产生的热从溅射传导到背板外部。非粘合性溅射结构还包括多个不粘合的紧固构件，其保持背板和溅射靶的相对表面彼此接触。非粘合的紧固构件延伸穿过背板的厚度并且对应于除了冷却构件之外的背板的区域。

40. 发明申请

US20120252527A1 APPARATUS AND METHOD FOR DETECTING PROXIMITY BY PROXIMITY SENSOR IN PORTABLE TERMINAL 有权
标题翻译：用便携式终端检测接近传感器接近的装置和方法
公开(公告)号：US20120252527A1
公开(公告)日：2012-10-04
申请号：US13436407
申请日：2012-03-30
申请人： Sang-Su Kim , Dong-Min Yoo , Tae-Woo Noh , Seung-Joo Hyun
发明人： Sang-Su Kim , Dong-Min Yoo , Tae-Woo Noh , Seung-Joo Hyun
IPC分类号： H04M1/00
CPC分类号： H04M1/67 , H03K17/941 , H04M2250/12
摘要： An apparatus and method is configured to detect the proximity of an object using a proximity sensor in a portable terminal. A method for detecting the proximity of an object in a portable terminal mounted with a proximity sensor includes setting a reference light-receiving quantity according to a hairstyle of a user of the portable terminal, emitting light, detecting a light-receiving quantity corresponding to the emitted light, and determining the proximity/non-proximity of an object by comparing the light-receiving quantity with the reference light-receiving quantity.
摘要翻译：一种装置和方法被配置为使用便携式终端中的接近传感器来检测物体的接近度。用于检测安装有接近传感器的便携式终端中的物体的接近度的方法包括根据便携式终端的用户的发型设置参考光接收量，发射光，检测对应于发射光，以及通过将光接收量与参考光接收量进行比较来确定对象的接近度/非接近度。

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