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31. 发明授权

US5951702A RAM-like test structure superimposed over rows of macrocells with added differential pass transistors in a CPU 失效
标题翻译：在CPU中添加有差分传输晶体管的宏单元行上叠加的类似RAM的测试结构
公开(公告)号：US5951702A
公开(公告)日：1999-09-14
申请号：US832922
申请日：1997-04-04
申请人： Hank Lim , Earl T. Cohen , Peter J. Vigil , Jengwei Pan , James S. Blomgren
发明人： Hank Lim , Earl T. Cohen , Peter J. Vigil , Jengwei Pan , James S. Blomgren
IPC分类号： G11C29/04 , G11C29/00 , C11C7/00
CPC分类号： G11C29/04
摘要： A test structure is added to a microprocessor. The test structure is a RAM-like array of scan-clock word lines which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines and the rows of macrocells are scan-data bit lines. Each testable macrocell has true and complement signal nodes that are connected to a pair of scan-data bit lines through a pair of n-channel pass transistors. The gates of the pass transistors are controlled by the scan-clock word line. The true and complement signal nodes are the cross-coupled inverters or gates in a latch. The latch is written or loaded by driving opposite data values onto the pair of scan-data bit lines when the pass transistors are activated by the scan-clock word line. The macrocells have random widths and thus do not form regular columns, so the columns of scan-data bit lines must be expanded to accommodate the various macrocell widths. Non-storage macrocells such as logic gates and buffers can be read but not written using the pass transistors connected to true and complement nodes in the macrocell. Reading causes a small voltage difference to be generated on the scan-data bit lines which is sensed by a sense amplifier. Only two n-channel transistors are added to a macrocell to make the macrocell testable. Thus testing is added with minimal area, cost, and delay to the macrocell.
摘要翻译：将测试结构添加到微处理器。测试结构是一个像RAM一样的扫描时钟字线阵列，它选择一行要读或写的宏单元。垂直于扫描时钟字线和宏单元的行是扫描数据位线。每个可测试的宏单元具有通过一对n沟道传输晶体管连接到一对扫描数据位线的真实和补码信号节点。传输晶体管的栅极由扫描时钟字线控制。真实和补码信号节点是锁存器中的交叉耦合的反相器或门。当通过晶体管被扫描时钟字线激活时，通过将相反的数据值驱动到扫描数据位线对上来写入或加载锁存器。宏单元具有随机宽度，因此不形成规则列，因此扫描数据位线的列必须被扩展以适应各种宏单元宽度。可以读取非存储宏单元，例如逻辑门和缓冲器，但不能使用连接到宏单元中的真和补节点的传输晶体管来写入。读取会在由读出放大器感测到的扫描数据位线上产生小的电压差。只有两个n沟道晶体管被添加到宏单元以使宏单元可测试。因此，对宏单元的面积，成本和延迟最小化。

32. 发明授权

US5781457A Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU 失效
标题翻译：在双ALU的矢量复用器中执行的两个指令集的合并/掩码，旋转/移位和布尔运算
公开(公告)号：US5781457A
公开(公告)日：1998-07-14
申请号：US649116
申请日：1996-05-14
申请人： Earl T. Cohen , James S. Blomgren , David E. Richter
发明人： Earl T. Cohen , James S. Blomgren , David E. Richter
IPC分类号： G06F7/575 , G06F7/76 , G06F7/38
CPC分类号： G06F7/764 , G06F7/575 , G06F7/762
摘要： A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs but applying a merge mask to the select inputs. A byte-spreader copies byte or 16-bit operands to 32-bits before being rotated and merged by the vectored mux. A rotator is used to rotate an operand before being applied to the data input of the vectored mux so that compound rotate-merge operations can be executed in a single step through the vectored mux. A carry flag may also be merged in during a multi-step bit-test instruction. Complex CISC instructions such as rotate-through-carry and shift-double are executed in multiple steps on the vectored mux. Intermediate results are stored in the multiplier-quotient temporary registers which are normally used for multiply and divide instructions. A RISC ALU using the vectored mux BLU is modified only slightly to support execution of CISC instructions. Merge, mask, rotate, shift, and Boolean operations of both RISC and CISC instruction sets are executed in the same ALU because of the inherent flexibility of the vectored mux architecture.
摘要翻译：布尔逻辑单元（BLU）具有向量多路复用器。布尔指令通过将操作数应用于选择输入而实际表信号到数据输入来执行。通过反转连接并将操作数输入到数据输入，但将合并掩码应用于选择输入来执行合并和掩码操作。字节扩展器将字节或16位操作数复制到32位，然后由矢量复用器旋转并合并。旋转器用于在施加到向量多路复用器的数据输入之前旋转操作数，以便可以通过向量多路复用器在单个步骤中执行复合旋转合并操作。进位标志也可以在多步位测试指令期间被合并。复杂的CISC指令，例如旋转进位和移位双精度在多个步骤中被执行。中间结果存储在通常用于乘法和除法指令的乘法器商临时寄存器中。使用向量复用器BLU的RISC ALU仅稍微修改以支持执行CISC指令。 RISC和CISC指令集的合并，掩码，旋转，移位和布尔运算都由相同的ALU执行，因为矢量多路复用器架构具有固有的灵活性。

33. 发明授权

US5664159A Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register 失效
标题翻译：通过使用单个断点寄存器的页面分区来仿真多个调试断点的方法
公开(公告)号：US5664159A
公开(公告)日：1997-09-02
申请号：US436136
申请日：1995-05-08
申请人： David E. Richter , James S. Blomgren
发明人： David E. Richter , James S. Blomgren
IPC分类号： G06F11/36 , G06F12/10
CPC分类号： G06F12/1027 , G06F11/3648 , G06F12/1036 , G06F12/109
摘要： A single breakpoint address register on a CPU is shared to emulate a plurality of breakpoint registers. A plurality of breakpoints are stored in an emulation area of main memory. One of these breakpoints is loaded into the single breakpoint register on the CPU. When a translation-lookaside buffer (TLB) on the CPU detects a page miss, a page miss handler activates a debug processing routine to determine if the faulting page contains one of the breakpoints. If the faulting page does contain a breakpoint, then this breakpoint is written to the single breakpoint register on the CPU. Any page in TLB is invalidated if it contained the old breakpoint that was overwritten by the new breakpoint in the single breakpoint register. Thus only one breakpoint can have a page translation in the TLB at any time, and the breakpoints are swapped in and out of single breakpoint register when the TLB entries are swapped. A TLB invalidate entry instruction finds the old breakpoint's TLB entry and invalidates it. When multiple breakpoints exist on a single page, then that page is divided into partial pages, with each partial page having just one breakpoint. The TLB entries contain upper and lower bounds fields to identify the extent of the partial page. A bit in the condition register is set when multiple breakpoints exist on the same page.
摘要翻译： CPU上的单个断点地址寄存器被共享以模拟多个断点寄存器。多个断点存储在主存储器的仿真区域中。其中一个断点被加载到CPU上的单个断点寄存器中。当CPU上的翻译后备缓冲区（TLB）检测到页面未命中时，页面未命中处理程序激活调试处理例程，以确定故障页是否包含其中一个断点。如果故障页面包含断点，则该断点将写入CPU上的单个断点寄存器。 TLB中的任何页面如果包含在单个断点寄存器中被新断点覆盖的旧断点，则无效。因此，只有一个断点可以在TLB中随时进行页面转换，并且当TLB条目交换时，断点在单个断点寄存器中进出交换。 TLB无效条目指令找到旧断点的TLB条目并使其失效。当单个页面上存在多个断点时，该页面被分为部分页面，每个部分页面只有一个断点。 TLB条目包含用于标识部分页面的范围的上限和下限字段。当同一页上存在多个断点时，条件寄存器中的一位置1。

34. 发明授权

US5634118A Splitting a floating-point stack-exchange instruction for merging into surrounding instructions by operand translation 失效
标题翻译：分离浮点堆栈交换指令，通过操作数转换合并到周围的指令中
公开(公告)号：US5634118A
公开(公告)日：1997-05-27
申请号：US419122
申请日：1995-04-10
申请人： James S. Blomgren
发明人： James S. Blomgren
IPC分类号： G06F9/30 , G06F9/315 , G06F9/318 , G06F9/40
CPC分类号： G06F9/30032 , G06F9/3004 , G06F9/30101 , G06F9/3013 , G06F9/30134 , G06F9/3017
摘要： A stack-register swap or exchange instruction is executed by splitting the exchange into two halves, and then each half is absorbed into a surrounding instruction by translating its source or destination operands. If one or both surrounding instructions are absent, then one or both halves of the exchange instruction are inserted into the pipeline as separate pipeline flows. When the surrounding instructions are stack-based, the stack operands are first converted to a destination and two source operands that specify a register by absolute number. A translation circuit then translates one of the operands of a surrounding instruction so the surrounding instruction's source is read from the exchange instruction's source, or so that the surrounding instruction's destination is written to the exchange instruction's destination, eliminating the need for processing a separate exchange instruction. Pipelining avoids the need for a temporary register to hold the swap data, since both the register are read early in the pipeline before either instruction over-writes the register.
摘要翻译：通过将交换分成两半来执行堆栈寄存器交换或交换指令，然后通过转换其源操作数或目标操作数将每个半部分吸收到周围的指令中。如果一个或两个周围的指令不存在，则交换指令的一个或两个半部分作为单独的流水线插入到流水线中。当周围的指令是基于堆栈的时候，堆栈操作数首先被转换为一个目的地，另外两个源操作数通过绝对数字来指定一个寄存器。翻译电路然后翻译周围指令的操作数之一，以便从交换指令的源读取周围指令的源，或者将周围指令的目的地写入交换指令的目的地，从而无需处理单独的交换指令。流水线避免了临时寄存器保存交换数据的需要，因为在任一指令重写寄存器之前，两个寄存器都在流水线中早期读取。

35. 发明授权

US5608886A Block-based branch prediction using a target finder array storing target sub-addresses 失效
标题翻译：基于块的分支预测，使用存储目标子地址的目标取景器阵列
公开(公告)号：US5608886A
公开(公告)日：1997-03-04
申请号：US298778
申请日：1994-08-31
申请人： James S. Blomgren , Earl T. Cohen , Brian R. Baird
发明人： James S. Blomgren , Earl T. Cohen , Brian R. Baird
IPC分类号： G06F9/318 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/322 , G06F9/3836 , G06F9/3861
摘要： A target finder array in the instruction cache contains a lower portion of the target address and a block encoding indicating if the target address is within the same 2K-byte block that the branch instruction is in, or if the target address is in the next or previous 2K-byte block. The upper portion of the target address, its block number, which corresponds to the starting address of a 2K block, is generated from the target finder simply by taking the upper portion or block number of the branch instruction and incrementing and decrementing it, and using the block encoding in the finder to select either the unmodified block number of the branch instruction, or the incremented or decremented block number of the branch instruction. The lower portion of the target address that was stored in the finder is concatenated with the selected block number to get the predicted target address. The target address can be predicted in parallel with reading an instruction out of the cache, making the target available at the same time the branch instruction is available, eliminating pipeline stalls for correctly predicted branches. The initially predicted target address in the finder is generated by a quick decode of the instruction and is written when the cache is loaded from memory. The initial prediction does not have to be accurate because branch resolution logic will update the finder on each branch resolution. Register indirect branches and exceptions may also be predicted. Two instruction sets may be accommodated by different block encodings to indicate the instruction set. By using the block encoding, the finder array is small and inexpensive.
摘要翻译：指令高速缓存中的目标取景器阵列包含目标地址的较低部分和指示目标地址是否在分支指令所在的相同2K字节块内的块编码，或者目标地址在下一个或以前的2K字节块。目标地址的上部，其对应于2K块的开始地址的块号，仅通过取出分支指令的上限或块号并从而从目标取景器生成，并使用取景器中的块编码以选择分支指令的未修改块号，或分支指令的递增或递减块号。存储在取景器中的目标地址的下部与所选块号连接以获得预测的目标地址。可以通过从缓存中读取指令并行地预测目标地址，使目标在分支指令可用的同时可用，消除正确预测分支的流水线停顿。取景器中初始预测的目标地址是通过指令的快速解码产生的，并在从存储器加载高速缓存时写入。初始预测不一定是准确的，因为分支分辨率逻辑将在每个分支分辨率上更新取景器。也可以预测注册间接分支和异常。可以通过不同的块编码来容纳两个指令集，以指示指令集。通过使用块编码，查找器阵列小而便宜。

36. 发明授权

US5548545A Floating point exception prediction for compound operations and variable precision using an intermediate exponent bus 失效
标题翻译：使用中间指数总线的复合运算和变量精度的浮点异常预测
公开(公告)号：US5548545A
公开(公告)日：1996-08-20
申请号：US375352
申请日：1995-01-19
申请人： Cheryl S. Brashears , James S. Blomgren
发明人： Cheryl S. Brashears , James S. Blomgren
IPC分类号： G06F7/57 , G06F7/38
CPC分类号： G06F7/483 , G06F7/49905
摘要： Exponents are first combined together, in a way that varies with the type of floating point operation. A single intermediate exponent result is placed on an intermediate exponent bus. This intermediate exponent is adjusted upwards for any carry-out from the operation on the mantissas, or downwards for any cancellation of leading mantissa bits, producing the final exponent result. The intermediate exponent on the intermediate exponent bus is also compared to a single criteria which is used for all types of floating point operations. Thus the compare logic may be simplified because only a single set of criteria is used for all types of operations. Alternately, the criteria may be varied depending upon the degree of precision used by all operations. Because the intermediate exponent is used, separate exponent adders are not necessary for the prediction unit and the floating point unit. Compound floating point operations may require more complex logic for combining the exponents. The more complex logic is needed to calculate the exponent for the result, so again no additional logic is needed for prediction. Only a single exponent is outputted to the intermediate exponent bus. Thus compound floating point operations may be accommodated simply with the modifications needed for the exponent combination logic.
摘要翻译：指数首先组合在一起，其方式随浮点运算的类型而变化。单个中间指数结果被放置在中间指数总线上。这个中间指数向上调整用于尾数操作的任何进位，或者向下调整前导尾数位的任何取消，产生最终指数结果。中间指数总线上的中间指数也与用于所有类型的浮点运算的单个标准进行比较。因此，可以简化比较逻辑，因为对于所有类型的操作仅使用一组标准。或者，可以根据所有操作使用的精度来改变标准。由于使用中间指数，因此预测单元和浮点单元不需要单独的指数加法器。复合浮点运算可能需要更复杂的逻辑来组合指数。需要更复杂的逻辑来计算结果的指数，所以再次没有额外的逻辑需要预测。只有一个指数输出到中间指数总线。因此，复合浮点运算可以简单地适应指数组合逻辑所需的修改。

37. 发明授权

US5481684A Emulating operating system calls in an alternate instruction set using a modified code segment descriptor 失效
标题翻译：使用修改的代码段描述符模拟替代指令集中的操作系统调用
公开(公告)号：US5481684A
公开(公告)日：1996-01-02
申请号：US277905
申请日：1994-07-20
申请人： David E. Richter , Jay C. Pattin , James S. Blomgren
发明人： David E. Richter , Jay C. Pattin , James S. Blomgren
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/455 , G06F12/02
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/30174 , G06F9/30185 , G06F9/30196 , G06F9/3822 , G06F9/45554 , G06F12/0292
摘要： The CISC architecture is extended to provide for segments that can hold RISC code rather than just CISC code. These new RISC code segments have descriptors that are almost identical to the CISC segment descriptors, and therefore these RISC descriptors may reside in the CISC descriptor tables. The global descriptor table in particular may have CISC code segment descriptors for parts of the operating system that are written in x86 CISC code, while also having RISC code segment descriptors for other parts of the operating system that are written in RISC code. An undefined or reserved bit within the descriptor is used to indicate which instruction set the code in the segment is written in. An existing user program may be written in CISC code, but call a service routine in an operating system that is written in RISC code. Thus existing CISC programs may be executed on a processor that emulates a CISC operating system using RISC code. A processor capable of decoding both the CISC and RISC instruction sets is employed. The switch from CISC to RISC instruction decoding is triggered when control is transferred to a new segment, and the segment descriptor indicates that the code within the segment is written in the alternate instruction set.
摘要翻译：扩展CISC架构以提供可以容纳RISC代码而不仅仅是CISC代码的段。这些新的RISC代码段具有与CISC段描述符几乎相同的描述符，因此这些RISC描述符可以驻留在CISC描述符表中。全局描述符表格可能具有用x86 CISC代码编写的操作系统部分的CISC代码段描述符，同时还具有用RISC代码编写的操作系统其他部分的RISC代码段描述符。描述符中的未定义或保留位用于指示段中的代码被写入哪个指令集。现有的用户程序可以用CISC代码写入，但是在以RISC代码编写的操作系统中调用服务程序。因此，可以在使用RISC代码模拟CISC操作系统的处理器上执行现有的CISC程序。采用能够解码CISC和RISC指令集的处理器。当控制转移到新的段时，从CISC切换到RISC指令解码被触发，段描述符指示段内的代码被写入替代指令集。

38. 发明授权

US5455909A Microprocessor with operation capture facility 失效
标题翻译：具有操作捕捉功能的微处理器
公开(公告)号：US5455909A
公开(公告)日：1995-10-03
申请号：US872913
申请日：1992-04-22
申请人： James S. Blomgren , Jimmy Bracking , David Richter , Francis Spahn
发明人： James S. Blomgren , Jimmy Bracking , David Richter , Francis Spahn
IPC分类号： G06F1/30 , G06F1/32 , G06F7/575 , G06F9/455 , G06F13/10 , G06F13/12 , G06F13/24 , G06F11/00
CPC分类号： G06F13/24 , G06F1/30 , G06F1/3203 , G06F13/105 , G06F13/126 , G06F7/575 , G06F9/45558 , G06F2009/45579 , G06F2207/3828 , G06F7/49994
摘要： The present invention provides a microprocessor with a special Operation Capture Facility (OCF) mechanism which enables "faulting" whenever there is (a) a memory access request to any one of a specified plurality of blocks of memory (b) a request to access any one of a plurality of specified I-O ports or (c) any one of a specified plurality of interrupts is activated. This OCF mechanism includes a plurality of special registers which store either (a) an I-O port address, (b) a memory address or (c) an interrupt number. Mask registers are provided which (1) mask bits in the special register, thereby providing the ability to fault on an entire block of I-O access requests or upon activation of any one of a block of interrupts and (2) indicate which type of interrupts should be faulted and to indicate whether I-O should be faulted on a byte, word or double word.
摘要翻译：本发明提供了一种具有特殊的操作捕获设施（OCF）机制的微处理器，每当存在（a）存储器访问请求到指定的多个存储块中的任一个（b）访问任何多个指定的IO端口中的一个或（c）指定的多个中断中的任何一个被激活。该OCF机制包括多个专用寄存器，其存储（a）I-O端口地址，（b）存储器地址或（c）中断号。提供掩码寄存器，其中（1）特殊寄存器中的掩码位，从而提供对IO访问请求的整个块的故障或在中断块中的任何一个激活时的能力，以及（2）指示哪种类型的中断应该错误，并指示IO是否应在字节，字或双字上发生故障。

39. 发明授权

US5325516A Processor system with dual clock 失效
标题翻译：处理器系统具有双时钟
公开(公告)号：US5325516A
公开(公告)日：1994-06-28
申请号：US848544
申请日：1992-03-09
申请人： James S. Blomgren , Mark Semmelmeyer , Tuan Luong , Gary Baum
发明人： James S. Blomgren , Mark Semmelmeyer , Tuan Luong , Gary Baum
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4217
摘要： The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e. the address status signal) generated by the CPU. The ADS and RDY signals must be modified in a first way if the CPU calls for a memory cycle at the beginning of a bus cycle and in a second way if the CPU calls for a memory cycle in the middle of a CPU cycle. The use of a CPU clock speed doubler in combination with a write-back cache achieves truly synergistic increases in system speed.
摘要翻译：本发明提供了一种用于在存储器总线的周期速度的多频道处在单个微处理器中操作CPU的装置。利用本发明，提供了第一和第二定时信号。第二定时信号的频率是第一定时信号的频率的倍数。将第二或快速定时信号提供给CPU，并将第一或更慢的定时信号提供给存储器子系统。总线接口单元插在CPU和存储器总线之间。该总线接口单元从存储器子系统接收RDY信号（即就绪信号），并在将其提供给CPU之前对其进行修改。来自存储器子系统的“就绪”信号在每个总线周期的很大部分处于未定义状态。由于在每个存储器访问期间至少发生两个CPU周期，因此总线接口单元必须确保CPU不会误解来自存储器子系统的就绪信号。总线接口单元还必须修改由CPU产生的ADS信号（即地址状态信号）。如果CPU在总线周期开始时要求存储器周期，并且如果CPU在CPU周期中要求存储器周期，则ADS和RDY信号必须以第一种方式进行修改。使用CPU时钟速度倍增器与回写缓存相结合，实现了系统速度的真正协同增长。

40. 发明授权

US5313606A System for detecting boundary cross-over of instruction memory space using reduced number of address bits 失效
标题翻译：用于使用减少的地址位数来检测指令存储器空间的边界交叉的系统
公开(公告)号：US5313606A
公开(公告)日：1994-05-17
申请号：US642977
申请日：1991-01-17
申请人： Tuan Luong , James S. Blomgren , Winnie Yu
发明人： Tuan Luong , James S. Blomgren , Winnie Yu
IPC分类号： G06F12/14
CPC分类号： G06F12/1441
摘要： An improved system for checking for segmentation violations counts the total number of bytes accessed from the control segment following a control transfer operation. If the count indicates that a part of an instruction is fetched from outside the control segment a limit exception occurs.
摘要翻译：用于检查分段违例的改进系统计数在控制传送操作之后从控制段访问的总字节数。如果计数指示从控制段外部取出指令的一部分，则发生极限异常。

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