专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07010626B2 DMA prefetch 失效
标题翻译： DMA预取
公开(公告)号：US07010626B2
公开(公告)日：2006-03-07
申请号：US11057454
申请日：2005-02-14
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.
摘要翻译：提供了一种用于将数据从系统存储器预取到计算机系统中用于直接存储器访问（DMA）机制的高速缓存的方法和装置。为处理器设置了DMA机制。检测到DMA机制的负载访问模式。基于负载访问模式预测至少一个潜在的数据负载。响应于该预测，在DMA命令请求数据之前，将数据从系统存储器预取到高速缓存。

32. 发明授权

US06697939B1 Basic block cache microprocessor with instruction history information 失效
标题翻译：具有指令历史信息的基本块缓存微处理器
公开(公告)号：US06697939B1
公开(公告)日：2004-02-24
申请号：US09477569
申请日：2000-01-06
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F900
CPC分类号： G06F9/3814 , G06F9/30174 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3861
摘要： A processor, data processing system, and a related method of execution are disclosed. The processor is suitable for receiving a set of instructions and organizing the set of instructions into an instruction group. The instruction group is then dispatched for execution. Upon executing the instruction group, instruction history information indicative of an exception event associated with the instruction group is recorded. Thereafter, the execution of the instruction is modified responsive to the instruction history information to prevent the exception event from occurring during a subsequent execution of the instruction group. The processor includes a storage facility such as an instruction cache, an L2 cache or a system memory, a cracking unit, and a basic block cache. The cracking unit is configured to receive a set of instructions from the storage facility. The cracking unit is adapted to organize the set of instructions into an instruction group.
摘要翻译：公开了一种处理器，数据处理系统和相关的执行方法。处理器适用于接收一组指令，并将该组指令组织到指令组中。然后调度指令组以执行。在执行指令组时，记录指示与指令组相关联的异常事件的指令历史信息。此后，响应于指令历史信息修改指令的执行，以防止在指令组的后续执行期间发生异常事件。处理器包括诸如指令高速缓存，L2高速缓存或系统存储器，破解单元和基本块高速缓存之类的存储设备。破裂单元被配置为从存储设施接收一组指令。裂解单元适于将该组指令组织成指令组。

33. 发明授权

US06662360B1 Method and system for software control of hardware branch prediction mechanism in a data processor 失效
标题翻译：数据处理器中硬件分支预测机制的软件控制方法与系统
公开(公告)号：US06662360B1
公开(公告)日：2003-12-09
申请号：US09407105
申请日：1999-09-27
申请人： Robert William Hay , James Allan Kahle , Brian R. Konigsburg , David Stephen Levitan , Balaram Sinharoy
发明人： Robert William Hay , James Allan Kahle , Brian R. Konigsburg , David Stephen Levitan , Balaram Sinharoy
IPC分类号： G06F944
CPC分类号： G06F9/3846 , G06F9/3848
摘要： A method and system is disclosed for software manipulation of hardware prediction mechanism in a data processor with software prediction. The hardware branch prediction mechanism is enhanced with at least two bits for path prediction. These bits are settable by a software and are capable of overriding the hardware branch prediction mechanism. Branch prediction information is encoded into a branch instruction in the software. This information includes a pre-determined value for each bit. Finally, a branch path of said instruction is predicted based on the value of the bits.
摘要翻译：公开了一种用于软件预测的数据处理器中硬件预测机制的软件操纵的方法和系统。用于路径预测的至少两个比特来增强硬件分支预测机制。这些位可由软件设置，并能够覆盖硬件分支预测机制。分支预测信息被编码成软件中的分支指令。该信息包括每个位的预定值。最后，基于比特的值来预测所述指令的分支路径。

34. 发明授权

US06629233B1 Secondary reorder buffer microprocessor 有权
标题翻译：二次重排缓冲微处理器
公开(公告)号：US06629233B1
公开(公告)日：2003-09-30
申请号：US09506527
申请日：2000-02-17
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F930
CPC分类号： G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method, processor, and data processing system for enabling maximum instruction issue despite the presence of complex instructions that require multiple rename registers is disclosed. The method includes allocating a first rename register from a first reorder buffer for storing the contents of a first register affected by the complex instruction. A second rename register from a second reorder buffer is then allocated for storing the contents of a second register affected by the complex instruction. In an embodiment in which the first reorder buffer supports a maximum number of allocations per cycle, the allocation of the second register using the second reorder buffer prevents the complex instruction from requiring multiple allocation slots in the first reorder buffer. The method may further include issuing a second instruction that contains a dependency on a register that is allocated in the secondary reorder buffer. In one embodiment, reorder buffer information indicating the second instruction's dependence on a register allocated in the secondary reorder buffer is associated with the second instruction such that, when the second instruction is issued subsequently, the reorder buffer information is used to restrict the issue unit to checking only the secondary reorder buffer for dependencies.
摘要翻译：公开了一种方法，处理器和数据处理系统，用于实现最大化指令发布，尽管存在需要多个重命名寄存器的复杂指令。该方法包括从第一重排序缓冲器分配第一重命名寄存器，用于存储受复合指令影响的第一寄存器的内容。然后分配来自第二重排序缓冲器的第二重命名寄存器用于存储受复合指令影响的第二寄存器的内容。在其中第一重排序缓冲器支持每个周期的最大分配数量的实施例中，使用第二重排序缓冲器分配第二寄存器防止复指令在第一重排序缓冲器中需要多个分配时隙。该方法还可以包括发出包含对在二次重排序缓冲器中分配的寄存器的依赖性的第二指令。在一个实施例中，指示第二指令对在二次重排序缓冲器中分配的寄存器的依赖性的重新排序缓冲器信息与第二指令相关联，使得当随后发出第二指令时，重排序缓冲器信息用于将发布单元限制为仅检查辅助重新排序缓冲区以获取依赖关系。

35. 发明授权

US06539500B1 System and method for tracing 失效
标题翻译：系统和追踪方法
公开(公告)号：US06539500B1
公开(公告)日：2003-03-25
申请号：US09428410
申请日：1999-10-28
申请人： James Allan Kahle , Alexander Erik Mericas , Kevin Franklin Reick , Joel M. Tendler
发明人： James Allan Kahle , Alexander Erik Mericas , Kevin Franklin Reick , Joel M. Tendler
IPC分类号： G06F1100
CPC分类号： G06F11/3636
摘要： The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by design to allow an instruction to execute and simultaneously to be stored and forwarded to shared memory operable as a trace buffer. Since each processor is general purpose, the trace routine necessary for tracing, can by one of the routines or programs that can be written and executed on either of the processors. One of the processors can run, collect and analyze the executed and store instructions of the other processor. Since the processors can be on a single chip the shared memory bus that writes and reads the executed instructions can operate at high speed. Also since the trace function is part of the multiprocessor architecture its speed of operation will scale with the speed of the processors without modification.
摘要翻译：本发明公开了一种用于在计算机系统中实现指令跟踪的系统和方法，特别是具有紧耦合的共享处理器中央处理器单元（CPU）的计算机系统。每个处理器通常是通过设计修改的目的处理器，以允许指令执行并同时被存储并转发到可用作跟踪缓冲器的共享存储器。由于每个处理器是通用目的，因此可以通过其中一个可以在任一处理器上编写和执行的程序之一进行跟踪所需的跟踪例程。其中一个处理器可以运行，收集和分析其他处理器的执行和存储指令。由于处理器可以在单个芯片上，写入和读取执行的指令的共享存储器总线可以高速运行。此外，由于跟踪功能是多处理器架构的一部分，因此操作速度将随着处理器的速度而不变化。

36. 发明授权

US5758140A Method and system for emulating instructions by performing an operation directly using special-purpose register contents 失效
标题翻译：通过直接使用专用寄存器内容进行操作来仿真指令的方法和系统
公开(公告)号：US5758140A
公开(公告)日：1998-05-26
申请号：US581793
申请日：1996-01-25
申请人： James Allan Kahle , Soummya Mallick
发明人： James Allan Kahle , Soummya Mallick
IPC分类号： G06F9/30 , G06F9/318 , G06F9/455 , G06F9/42
CPC分类号： G06F9/30167 , G06F9/30174
摘要： A system and method for improving the performance of a processor that emulates a guest instruction where the guest instruction includes a first and second operand. The first operand is stored in a general purpose register, and the second operand is stored in a special-purpose register. The method and system provides a host instruction that performs an operation using the first operand and the second operand without moving the second operand from the special-purpose register into the general purpose register. This reduces the number of instructions in the semantic routines necessary to operate on immediate data from guest instructions and increases emulation performance.
摘要翻译：一种用于提高仿真访客指令的处理器的性能的系统和方法，其中所述访客指令包括第一和第二操作数。第一个操作数存储在通用寄存器中，第二个操作数存储在专用寄存器中。该方法和系统提供主机指令，其使用第一操作数和第二操作数执行操作，而不将第二操作数从专用寄存器移动到通用寄存器中。这减少了从客户指令对即时数据进行操作所需的语义程序中的指令数量，并增加了仿真性能。

37. 发明授权

US5758120A Method and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bits 失效
标题翻译：在多处理器计算机系统中，利用参考和更改位的并发访问来增加系统存储器并发性的方法和系统
公开(公告)号：US5758120A
公开(公告)日：1998-05-26
申请号：US700132
申请日：1996-08-20
申请人： James Allan Kahle , John Stephen Muhich , Richard Raphael Oehler , Edward John Silha
发明人： James Allan Kahle , John Stephen Muhich , Richard Raphael Oehler , Edward John Silha
IPC分类号： G06F15/16 , G06F12/10 , G06F15/177
CPC分类号： G06F12/1009 , G06F12/1027
摘要： A method and system for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instructions and for performing read, write and store operations and an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses within the system memory. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields, an effective address and an associated real memory address for a selected system memory location. A reference bit is provided within a first individually accessible field in each page table entry and this reference bit is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and this change bit is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate accessible fields the reference bit and change bit may be concurrently updated by multiple processors, increasing memory concurrency.
摘要翻译：一种用于在多处理器计算机系统中增加存储器并发性的方法和系统，其包括系统存储器，经由总线耦合在一起的多个处理器，每个处理器包括用于执行多个指令并用于执行读取，写入和存储操作的多个处理器单元以及相关联的翻译后备缓冲区（TLB），用于将有效地址转换为系统内存中的实际内存地址。在系统存储器内的页表内提供多个页表条目，每个页表格包括多个单独可访问的字段，一个有效地址和一个所选系统存储器位置的相关实际存储器地址。参考位提供在每个页表项中的第一单独可访问字段内，并且该参考位用于指示是否已经为读或写操作访问了相关联的系统存储器位置。在每个页表条目内的第二单独可访问字段内提供变更位，并且该改变位用于指示相关联的系统存储器位置是否已被写入操作修改。通过将参考位和更改位存储在单独的可访问字段中，参考位和更改位可以由多个处理器同时更新，从而增加内存并发性。

38. 发明授权

US5732235A Method and system for minimizing the number of cycles required to execute semantic routines 失效
标题翻译：用于最小化执行语义例程所需的周期数的方法和系统
公开(公告)号：US5732235A
公开(公告)日：1998-03-24
申请号：US591291
申请日：1996-01-25
申请人： James Allan Kahle , Soummya Mallick , Larry Bryce Phillips , Russell Adley Reininger
发明人： James Allan Kahle , Soummya Mallick , Larry Bryce Phillips , Russell Adley Reininger
IPC分类号： G06F9/318 , G06F9/30
CPC分类号： G06F9/30174 , G06F9/3879 , G06F9/45504
摘要： A system and method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions. Each of the semantic routines includes a block of host instructions for performing the function of the corresponding guest instruction, and the last instruction in each of the semantic routines is a branch instruction. The method and system first determines the block length of each of the semantic routines. When a first guest instruction is encountered, the block of instructions in a first semantic routine corresponding to a guest instruction is executed. The block length of first semantic routine is then used to determine when to fetch a second semantic routine without fetching and decoding the branch instruction in the first semantic routine, thereby increasing emulation performance.
摘要翻译：一种用于减少在模拟客户指令的处理器中执行语义例程所需的周期时间的系统和方法。每个语义例程包括用于执行相应来宾指令的功能的主机指令块，并且每个语义例程中的最后一条指令是分支指令。该方法和系统首先确定每个语义例程的块长度。当遇到第一访客指令时，执行对应于访客指令的第一语义程序中的指令块。然后，第一语义例程的块长度用于确定何时获取第二语义例程而不在第一语义例程中取出和解码分支指令，从而增加仿真性能。

39. 发明授权

US5732005A Single-precision, floating-point register array for floating-point units performing double-precision operations by emulation 失效
标题翻译：用于通过仿真执行双精度操作的浮点单元的单精度浮点寄存器阵列
公开(公告)号：US5732005A
公开(公告)日：1998-03-24
申请号：US386980
申请日：1995-02-10
申请人： James Allan Kahle , Tai Dinh Ngo , Aubrey Deene Ogden , Michael Putrino , Johm Victor Sell
发明人： James Allan Kahle , Tai Dinh Ngo , Aubrey Deene Ogden , Michael Putrino , Johm Victor Sell
IPC分类号： G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F7/483 , G06F2207/382
摘要： A single-precision floating-point register array for a floating-point execution unit that performs double-precision operations by emulation is provided. The register array comprises a plurality of single-precision floating-point registers and a storage device that stores one or more status bits in association with each of the plurality of registers; the status bits associated with each register indicate either that the associated data register contains single-precision or integer data, or that the data for the associated register is contained in an emulated register in memory that is mapped to the associated register. When a register is a source for an operation, the status bits associated with the register are checked and the required operand data for that register is read from the register or from an emulated register mapped to that register, as a function of the state of the status bits.
摘要翻译：提供了一种用于通过仿真执行双精度操作的浮点执行单元的单精度浮点寄存器阵列。寄存器阵列包括多个单精度浮点寄存器和与多个寄存器中的每一个相关联地存储一个或多个状态位的存储器件; 与每个寄存器相关联的状态位指示相关联的数据寄存器包含单精度或整数数据，或者相关联寄存器的数据包含在映射到相关寄存器的存储器中的仿真寄存器中。当寄存器是操作的源时，检查与寄存器相关联的状态位，并且从寄存器或映射到该寄存器的仿真寄存器读取该寄存器所需的操作数数据，作为该寄存器状态的函数状态位。

40. 发明授权

US07802023B2 Methods and apparatus for supporting multiple configurations in a multi-processor system 有权
标题翻译：在多处理器系统中支持多种配置的方法和装置
公开(公告)号：US07802023B2
公开(公告)日：2010-09-21
申请号：US11250246
申请日：2005-10-14
申请人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
发明人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00 , G06F13/42
CPC分类号： G06F12/0815 , G06F12/0835
摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
摘要翻译：方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式