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31. 发明授权

US06906905B1 Micro electro-mechanical variable capacitor 失效
标题翻译：微机电可变电容器
公开(公告)号：US06906905B1
公开(公告)日：2005-06-14
申请号：US10710283
申请日：2004-06-30
申请人： Anil K. Chinthakindi
发明人： Anil K. Chinthakindi
IPC分类号： H01G5/00 , H01G5/18
CPC分类号： H01G5/18
摘要： A three-dimensional micro electro-mechanical (MEMS) variable capacitor is described wherein movable comb electrodes of opposing polarity are fabricated simultaneously on the same substrate are independently actuated. These electrodes are formed in an interdigitated fashion to maximize the capacitance of the device. The electrodes are jointly or individually actuated. A separate actuation electrode and a ground plane electrode actuate the movable electrodes. The voltage potential between the two electrodes provides a primary mode of operation of the device. The variation of the sidewall overlap area between the interdigitated fingers provides the expected capacitance tuning of the device. The interdigitated electrodes can also be attached on both ends to form fixed-fixed beams. The stiffness of the electrodes is reduced by utilizing thin support structures at the ends of the electrodes. The three dimensional aspect of the device avails large surface area. Large capacitance variation and tuning ranges are obtained by independent actuation of the electrode fingers. A plurality of modes of operation of the device provides wide flexibility and greater performance advantage for the device. Upon fabrication of the device, a separate substrate with etched dielectric is used to encapsulated the device. The MEMS device is then completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale, an improved device yield is obtained at a lower cost.
摘要翻译：描述了三维微机电（MEMS）可变电容器，其中在相同基板上同时制造相反极性的可动梳状电极被独立地致动。这些电极以交错方式形成，以使器件的电容最大化。电极共同或单独致动。单独的致动电极和接地平面电极致动可动电极。两个电极之间的电压电位提供了器件的主要操作模式。交叉指状物之间的侧壁重叠区域的变化提供了设备的预期电容调谐。交叉电极也可以安装在两端以形成固定的光束。通过在电极的端部利用薄的支撑结构来减小电极的刚度。该装置的三维方面具有较大的表面积。通过电极指的独立致动获得大的电容变化和调谐范围。器件的多种操作模式为器件提供了广泛的灵活性和更大的性能优势。在制造器件时，使用具有蚀刻电介质的单独衬底来封装器件。然后，MEMS器件被完全封装，不需要额外的器件封装。此外，由于可以在晶片规模上进行取向和接合，所以可以以更低的成本获得提高的器件产量。

32. 发明授权

US06661069B1 Micro-electromechanical varactor with enhanced tuning range 有权
标题翻译：具有增强调谐范围的微机电变容二极管
公开(公告)号：US06661069B1
公开(公告)日：2003-12-09
申请号：US10278211
申请日：2002-10-22
申请人： Anil K. Chinthakindi , Robert A. Groves , Kenneth J. Stein , Seshadri Subbanna , Richard P. Volant
发明人： Anil K. Chinthakindi , Robert A. Groves , Kenneth J. Stein , Seshadri Subbanna , Richard P. Volant
IPC分类号： H01L2986
CPC分类号： H01G5/18 , B81B2201/01 , H01G5/011 , Y10S257/924
摘要： A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.
摘要翻译：描述了三维微机电（MEM）变容二极管，其中可移动光束和固定电极分别制造在彼此耦合的分开的基板上。具有梳状驱动电极的可移动光束在“芯片侧”上制造，而固定底部电极制造在分离的基板“载体侧”上。在衬底的两个表面上制造器件时，芯片侧器件被切割并“翻转”，对准并接合到“载体”衬底以形成最终器件。梳状驱动（鳍）电极用于致动，同时电极的运动提供电容的变化。由于所涉及的驱动力恒定，可以获得大的电容调谐范围。该装置的三维方面具有较大的表面积。当提供大的纵横比特征时，可以使用较低的致动电压。在制造时，MEMS器件被完全封装，不需要额外的器件封装。此外，由于可以在晶片规模（晶片级MEMS封装）上进行取向和接合，所以可以以更低的成本获得改进的器件产量。

33. 发明授权

US08487401B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08487401B2
公开(公告)日：2013-07-16
申请号：US13359634
申请日：2012-01-27
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L23/522
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

34. 发明授权

US08207568B2 Process for single and multiple level metal-insulator-metal integration with a single mask 有权
标题翻译：单层和多层金属绝缘体金属与单一掩模集成的工艺
公开(公告)号：US08207568B2
公开(公告)日：2012-06-26
申请号：US11162661
申请日：2005-09-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/92
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：制造MIM电容器和MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

35. 发明授权

US08119491B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08119491B2
公开(公告)日：2012-02-21
申请号：US12106374
申请日：2008-04-21
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L21/20
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

36. 发明授权

US07768055B2 Passive components in the back end of integrated circuits 失效
标题翻译：集成电路后端的被动元件
公开(公告)号：US07768055B2
公开(公告)日：2010-08-03
申请号：US11164634
申请日：2005-11-30
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
IPC分类号： H01L29/94
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译：通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

37. 发明授权

US07670921B2 Structure and method for self aligned vertical plate capacitor 失效
标题翻译：自对准立板电容器的结构和方法
公开(公告)号：US07670921B2
公开(公告)日：2010-03-02
申请号：US11616955
申请日：2006-12-28
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Richard P. Volant
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Richard P. Volant
IPC分类号： H01L21/4763
CPC分类号： H01G4/33 , H01G4/005 , H01L23/5223 , H01L28/90 , H01L2924/0002 , Y10T29/417 , H01L2924/00
摘要： A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.
摘要翻译：形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在其中形成第一平面介质层和第一金属化层; 在其顶部形成第一钝化层; 在所述第一钝化层上形成平面导电层; 在指定区域中图案化和选择性地去除导电层直到第一钝化层以形成一组导电特征; 用高强度电介质涂层构图和保形地涂覆该组导电特征和暴露的第一钝化层; 在所述第一钝化层上设置第二电介质层并且包围所述一组导电特征; 图案化和选择性地去除第二衬底的部分以形成沟道和沟槽; 执行双镶嵌工艺以在沟槽和通道中形成第二金属化层，并在高强度电介质涂层上形成上导电表面。

38. 发明授权

US07585722B2 Integrated circuit comb capacitor 有权
标题翻译：集成电路梳状电容
公开(公告)号：US07585722B2
公开(公告)日：2009-09-08
申请号：US11306746
申请日：2006-01-10
申请人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
发明人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
摘要翻译：本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

39. 发明授权

US07566593B2 Fuse structure including cavity and methods for fabrication thereof 失效
标题翻译：保险丝结构，包括腔体及其制造方法
公开(公告)号：US07566593B2
公开(公告)日：2009-07-28
申请号：US11538170
申请日：2006-10-03
申请人： Anil K. Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Anil K. Chinthakindi , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
摘要翻译：熔丝结构包括插入在基板和熔丝材料层之间的空腔。空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。空隙由支撑熔丝材料层的一对牺牲层基座分开。通过使用封装介电层将空隙封装以形成空腔。或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。

40. 发明申请

US20090065898A1 INTEGRATED BEOL THIN FILM RESISTOR 有权
标题翻译：集成波形薄膜电阻器
公开(公告)号：US20090065898A1
公开(公告)日：2009-03-12
申请号：US12271942
申请日：2008-11-17
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L29/00
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译：在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

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