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31. 发明授权

US06455336B1 Power reduction method and design technique for burn-in 失效
标题翻译：降耗方法和烧录设计技术
公开(公告)号：US06455336B1
公开(公告)日：2002-09-24
申请号：US09682381
申请日：2001-08-27
申请人： Zachary E. Berndlmaier , Mark R. Bilak , Norman J. Rohrer
发明人： Zachary E. Berndlmaier , Mark R. Bilak , Norman J. Rohrer
IPC分类号： H01L2166
CPC分类号： G01R31/2879 , G01R31/2856
摘要： A design and burn-in technique that effectively reduces power consumption during burn-in for devices with high power consumption as a result of shrinking voltages, high instantaneous current, subthreshold leakage and high currents at stress conditions. Three methods of reducing power consumption during burn-in are disclosed in detail: (1) completely separate power grids, (2) isolated grids during burn-in, and (3) isolated grids for MTCMOS used during burn-in. Each technique provides a method of segmenting the power supply of a chip and controlling which segment of the chip is stressed based on which segment is ‘powered on’. Those segments not being stressed are ‘shutoff’ so as to reduce power consumption.
摘要翻译：一种设计和老化技术，可以有效降低由于电压缩减，高瞬时电流，亚阈值泄漏和应力条件下的高电流而导致高功耗器件老化过程中的功耗。详细介绍了三种降低老化过程中功耗的方法：（1）完全分离电网，（2）老化期间的隔离栅格，（3）老化过程中使用的MTCMOS隔离网格。每种技术提供了一种分割芯片的电源的方法，并且基于哪个部分被“通电”来控制芯片的哪个片段被应力，那些不受应力的片段是“关闭”，以便降低功耗。

32. 发明授权

US07450413B2 Configurable SRAM system and method 有权
标题翻译：可配置的SRAM系统和方法
公开(公告)号：US07450413B2
公开(公告)日：2008-11-11
申请号：US11463917
申请日：2006-08-11
申请人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
发明人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译：静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。

33. 发明授权

US07194714B2 Method of reducing instantaneous current draw and an integrated circuit made thereby 失效
标题翻译：降低瞬时电流消耗的方法和由此制成的集成电路
公开(公告)号：US07194714B2
公开(公告)日：2007-03-20
申请号：US10605683
申请日：2003-10-17
申请人： Paul D. Kartschoke , Norman J. Rohrer
发明人： Paul D. Kartschoke , Norman J. Rohrer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method utilizing available timing slack in the various timing paths of a synchronous integrated circuit to reduce the overall instantaneous current draw across the circuit. In the method, each timing path is analyzed to determine its late mode margin or its late mode margin and early mode margin. A delay is added to each timing path having a late mode margin greater than zero. Each delay effectively shifts the peak current draw for the corresponding timing path within each clock cycle so that the peaks do not occur simultaneously across all timing paths. In other embodiments, the peak overall instantaneous current draw can be further reduced by reducing the delay in some of the delayed timing paths.
摘要翻译：一种在同步集成电路的各种定时路径中利用可用的定时松弛的方法来减少整个电路上的总瞬时电流消耗。在该方法中，分析每个定时路径以确定其延迟模式余量或其延迟模式余量和早期模式余量。延迟增加到具有大于零的延迟模式余量的每个定时路径。每个延迟有效地移动每个时钟周期内对应的时序路径的峰值电流消耗，使得峰值不会在所有定时路径上同时发生。在其他实施例中，可以通过减少一些延迟定时路径中的延迟来进一步减小峰值总瞬时电流消耗。

34. 发明授权

US07058531B2 Temperature compensation in maximum frequency measurement and speed sort 失效
标题翻译：最大频率测量和速度排序时的温度补偿
公开(公告)号：US07058531B2
公开(公告)日：2006-06-06
申请号：US10708916
申请日：2004-03-31
申请人： Jennifer E. Appleyard , Troy Carlson , Joseph M. Forbes , Dean G. Percy , Norman J. Rohrer , William J. Tanona
发明人： Jennifer E. Appleyard , Troy Carlson , Joseph M. Forbes , Dean G. Percy , Norman J. Rohrer , William J. Tanona
IPC分类号： G01K15/00
CPC分类号： G01K7/00
摘要： A method is disclosed of temperature compensation for measurement of a temperature sensitive parameter of semiconductor IC chips, particularly temperature compensation for a maximum frequency measurement (Fmax) and speed sort/categorization of semiconductor IC chips. The method includes determining a change of a temperature sensitive parameter of the chip with temperature; measuring the temperature sensitive parameter of the chip during testing of the chip; measuring the chip temperature directly during or following the measurement of the temperature sensitive parameter; and determining an adjusted temperature sensitive parameter of the chip based upon the measured temperature sensitive parameter of the chip during testing, the measured chip temperature, and the determined change of the temperature sensitive parameter of the chip with temperature.
摘要翻译：公开了用于测量半导体IC芯片的温度敏感参数的温度补偿的方法，特别是用于最大频率测量（Fmax）的温度补偿和半导体IC芯片的速度分类/分类。该方法包括用温度确定芯片的温度敏感参数的变化; 在芯片测试期间测量芯片的温度敏感参数; 在温度敏感参数测量期间或之后直接测量芯片温度; 以及基于所测量的芯片在测试期间的温度敏感参数，测量的芯片温度以及所确定的具有温度的芯片的温度敏感参数的变化来确定芯片的调节的温度敏感参数。

35. 发明授权

US08607080B2 Optimizing voltage on a power plane using a host control unit to control a networked voltage regulation module array 有权
标题翻译：使用主机控制单元优化电源平面上的电压，以控制网络电压调节模块阵列
公开(公告)号：US08607080B2
公开(公告)日：2013-12-10
申请号：US13399799
申请日：2012-02-17
申请人： Gilles Gervais , Alain Loiseau , Kirk D. Peterson , Norman J. Rohrer
发明人： Gilles Gervais , Alain Loiseau , Kirk D. Peterson , Norman J. Rohrer
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
摘要翻译：提出了一种使用网络化的三维电压调节模块阵列（VRM）来实时优化电压岛上部件功率使用的方法，系统和计算机程序。联网的VRM设备并行工作，为连接的电压岛提供足够的电力，并补充系统中可能需要额外功率的重要事件的其他VRM。

36. 发明授权

US08341434B2 Optimizing voltage on a power plane using a networked voltage regulation module array 失效
标题翻译：使用网络电压调节模块阵列优化电源平面上的电压
公开(公告)号：US08341434B2
公开(公告)日：2012-12-25
申请号：US12037743
申请日：2008-02-26
申请人： Gilles Gervais , Alain Loiseau , Kirk D. Peterson , Norman J. Rohrer
发明人： Gilles Gervais , Alain Loiseau , Kirk D. Peterson , Norman J. Rohrer
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
摘要翻译：提出了一种使用网络化的三维电压调节模块阵列（VRM）来实时优化电压岛上部件功率使用的方法，系统和计算机程序。联网的VRM设备并行工作，为连接的电压岛提供足够的电力，并补充系统中可能需要额外功率的重要事件的其他VRM。

37. 发明授权

US07715222B2 Configurable SRAM system and method 失效
标题翻译：可配置的SRAM系统和方法
公开(公告)号：US07715222B2
公开(公告)日：2010-05-11
申请号：US12210712
申请日：2008-09-15
申请人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
发明人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译：静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。

38. 发明授权

US07681153B2 Estimating static power consumption of integrated circuits using logic gate templates 失效
标题翻译：使用逻辑门模板估算集成电路的静态功耗
公开(公告)号：US07681153B2
公开(公告)日：2010-03-16
申请号：US11626020
申请日：2007-01-23
申请人： Cedric Lichtenau , Alberto Garcia-Ortiz , Norman J. Rohrer
发明人： Cedric Lichtenau , Alberto Garcia-Ortiz , Norman J. Rohrer
IPC分类号： G06F17/50
CPC分类号： G01R31/2837
摘要： A method, system and computer program product for estimating a static power consumption of an integrated circuit are disclosed. The static power consumption of a cell of the integrated circuit is characterized based on contributions of an input node(s) and an output node(s) of the cell. A contribution considers a leakage weight and a leakage probability of a node. A logic template of the cell may be created to better represent a contribution of an internal node to the static power consumption of the cell.
摘要翻译：公开了一种用于估计集成电路的静态功耗的方法，系统和计算机程序产品。基于单元的输入节点和输出节点的贡献来表征集成电路的单元的静态功耗。贡献考虑了节点的泄漏重量和泄漏概率。可以创建小区的逻辑模板以更好地表示内部节点对小区的静态功耗的贡献。

39. 发明申请

US20090141536A1 Structure for a Configurable SRAM System and Method 有权
标题翻译：可配置SRAM系统和方法的结构
公开(公告)号：US20090141536A1
公开(公告)日：2009-06-04
申请号：US11947092
申请日：2007-11-29
申请人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
发明人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , G11C11/413
摘要： A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译：静态随机存取存储器（SRAM）电路的设计结构包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。

40. 发明申请

US20080037313A1 CONFIGURABLE SRAM SYSTEM AND METHOD 有权
标题翻译：可配置的SRAM系统和方法
公开(公告)号：US20080037313A1
公开(公告)日：2008-02-14
申请号：US11463917
申请日：2006-08-11
申请人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
发明人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译：静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。

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