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31. 发明授权

US08993407B2 Compact localized RRAM cell structure realized by spacer technology 有权
标题翻译：通过间隔技术实现紧凑的局部RRAM单元结构
公开(公告)号：US08993407B2
公开(公告)日：2015-03-31
申请号：US13683779
申请日：2012-11-21
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2445 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1675 , H01L45/1691
摘要： An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode.
摘要翻译：公开了一种具有垂直BJT选择器的RRAM。实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域的底部周围和下方形成第一极性，在STI区域的相对侧上的阱上的第二极性沟道，以及第一在衬底的表面上的每个通道上的极性有源区域，在有源区域和STI区域上形成RRAM衬垫，在RRAM衬垫上形成牺牲顶部电极，在牺牲顶部电极的相对侧上形成间隔物，注入第二极性在牺牲顶部电极的相对侧上的有源区域中形成掺杂剂，在间隔物附近形成氧化硅，去除形成空腔的牺牲顶部电极的至少一部分，在空腔中形成邻近间隔物的内部间隔物和顶部电极。

32. 发明申请

US20140167161A1 FLOATING BODY CELL 有权
标题翻译：浮动体细胞
公开(公告)号：US20140167161A1
公开(公告)日：2014-06-19
申请号：US13713393
申请日：2012-12-13
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7841 , H01L29/66545 , H01L29/78654
摘要： Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions.
摘要翻译：公开了具有更快编程和更低刷新率的浮体单元（FBC）的形成方法以及所得到的器件。实施例包括在基板上形成绝缘体上硅（SOI）层; 形成围绕和/或在SOI层上的带工程层; 形成源极区域和漏极区域，所述源极区域和漏极区域中的至少一个在所述带状工程化层上; 以及在SOI层上，在源区和漏区之间形成栅极。

33. 发明授权

US08536558B1 RRAM structure with improved memory margin 有权
标题翻译： RRAM结构具有改善的记忆余量
公开(公告)号：US08536558B1
公开(公告)日：2013-09-17
申请号：US13562646
申请日：2012-07-31
申请人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L47/00
CPC分类号： H01L45/146 , H01L45/04 , H01L45/124 , H01L45/1683
摘要： Resistive random-access memory (RRAM) structures are formed with ultra-thin RRAM-functional layers, thereby improving memory margins. Embodiments include forming an interlayer dielectric (ILD) over a bottom electrode, forming a sacrificial layer over the ILD, removing a portion of the ILD and a portion of the sacrificial layer vertically contiguous with the portion of the ILD, forming a cell area, forming a metal layer within the cell area, forming an interlayer dielectric structure above or surrounded by and protruding above the metal layer, a top surface of the interlayer dielectric structure being coplanar with a top surface of the sacrificial layer, removing the sacrificial layer, forming a memory layer on the ILD and/or on side surfaces of the interlayer dielectric structure, and forming a dielectric layer surrounding at least a portion of the interlayer dielectric structure.
摘要翻译：电阻随机存取存储器（RRAM）结构由超薄的RRAM功能层组成，从而提高存储容量。实施例包括在底部电极上形成层间电介质（ILD），在ILD上形成牺牲层，去除ILD的一部分和与ILD的部分垂直邻接的部分牺牲层，形成细胞区域，形成细胞区域在所述电池区域内的金属层，在所述金属层的上方或之上形成层间电介质结构，所述层间电介质结构与所述牺牲层的顶表面共平面，去除所述牺牲层，形成在层间电介质结构的ILD和/或侧表面上的存储层，以及形成围绕至少一部分层间电介质结构的电介质层。

34. 发明申请

US20130221308A1 COMPACT RRAM DEVICE AND METHODS OF MAKING SAME 有权
标题翻译：紧凑的RRAM设备及其制造方法
公开(公告)号：US20130221308A1
公开(公告)日：2013-08-29
申请号：US13408221
申请日：2012-02-29
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.
摘要翻译：这里公开了紧凑的RRAM（电阻随机存取存储器）装置结构和制造这种RRAM装置的各种方法。在一个示例中，本文公开的器件包括栅极，导电侧壁隔离物和位于栅电极和导电侧壁间隔物之间的至少一个可变电阻材料层。

35. 发明授权

US08440533B2 Self-aligned contact for replacement metal gate and silicide last processes 有权
标题翻译：用于替换金属栅极和硅化物最后工艺的自对准触点
公开(公告)号：US08440533B2
公开(公告)日：2013-05-14
申请号：US13041134
申请日：2011-03-04
申请人： Eng Huat Toh , Elgin Quek
发明人： Eng Huat Toh , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L27/088 , H01L21/28518 , H01L21/76801 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L21/823475 , H01L29/78
摘要： A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.
摘要翻译：高K /金属栅极半导体器件具有较大的自对准触点，电阻降低。实施例包括在源极/漏极区域之间的衬底上形成第一高k金属栅极堆叠，在STI区域上形成第二高k金属栅极堆叠以及在金属栅极堆叠之间形成第一ILD，形成蚀刻停止层和在衬底上顺序地具有第二ILD，在金属栅堆叠上的第二ILD中具有开口，在开口的边缘上形成间隔物，在第二ILD和间隔物上形成第三ILD，在源/漏区上去除第一ILD 在邻近间隔物的源极/漏极区域上以及在间隔物的一部分上方去除蚀刻停止层，第二ILD和第三ILD，形成第一沟槽，在第二高k金属栅极上去除第三ILD 堆叠和一部分间隔物，形成第二沟槽，并在第一和第二沟槽中形成接触。

36. 发明申请

US20130037877A1 DOUBLE GATED FLASH MEMORY 有权
标题翻译：双重放置闪存
公开(公告)号：US20130037877A1
公开(公告)日：2013-02-14
申请号：US13206780
申请日：2011-08-10
申请人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0425 , G11C16/14 , G11C16/26 , H01L21/28273 , H01L29/42328 , H01L29/66795 , H01L29/66825 , H01L29/7851 , H01L29/7881
摘要： A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.
摘要翻译：在存储器栅极堆叠和选择栅极之间制造具有鳍结构的分离栅极存储器单元。实施例包括存储器栅极堆叠下方的第一沟道区域和选择栅极下方的第二沟道区域。

37. 发明授权

US09093551B2 Method and apparatus for embedded NVM utilizing an RMG process 有权
标题翻译：使用RMG过程的嵌入式NVM的方法和装置
公开(公告)号：US09093551B2
公开(公告)日：2015-07-28
申请号：US13543340
申请日：2012-07-06
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/28 , H01L27/115 , H01L29/66
CPC分类号： H01L21/823437 , H01L21/28273 , H01L21/823425 , H01L21/823468 , H01L27/11524 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with RMG processes. Embodiments include forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate, forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures, forming an ILD adjacent to an exposed sidewall of each spacer, removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers, and forming a HKMG in the first cavity, wherein the HKMG forms an access gate.
摘要翻译：通过将嵌入式非易失性存储器（eNVM）与RMG进程集成来制造存储器件。实施例包括在衬底的上表面上形成第一和第二双多晶硅栅堆叠结构，在第一和第二双多晶硅栅叠层结构中的每一个的相对侧壁上形成间隔物，形成与暴露的侧壁相邻的ILD 去除所述第一双多晶硅栅叠层结构，在所述间隔物之间形成第一空腔，并在所述第一腔中形成HKMG，其中所述HKMG形成存取栅。

38. 发明授权

US09029231B2 Fin selector with gated RRAM 有权
标题翻译：翅片选择器与门控RRAM
公开(公告)号：US09029231B2
公开(公告)日：2015-05-12
申请号：US13795894
申请日：2013-03-12
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L21/20 , H01L45/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/146 , H01L45/1666
摘要： A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.
摘要翻译：公开了一种制造具有门控RRAM的翅片选择器和所产生的装置的方法。实施例包括在半导体衬底上形成底电极层和硬掩模; 蚀刻硬掩模，底电极层和半导体衬底以形成鳍状结构; 分别在所述鳍状结构的第一和第二侧表面上形成第一和第二虚拟栅极堆叠; 在所述第一和第二虚拟栅极堆叠的垂直表面上形成间隔物; 形成围绕所述间隔物的ILD; 去除所述第一和第二伪栅极堆叠，在所述鳍状结构的第一和第二侧上形成第一和第二空腔; 在所述第一和第二腔中的鳍状结构的第一和第二侧表面上分别形成RRAM层; 以及用顶部电极填充第一和第二腔中的每一个。

39. 发明授权

US09029227B2 P-channel flash with enhanced band-to-band tunneling hot electron injection 有权
标题翻译： P通道闪存具有增强的带对带隧道热电子注入
公开(公告)号：US09029227B2
公开(公告)日：2015-05-12
申请号：US13038081
申请日：2011-03-01
申请人： Eng Huat Toh , Elgin Quek , Ying Keung Leung , Sanford Chu
发明人： Eng Huat Toh , Elgin Quek , Ying Keung Leung , Sanford Chu
IPC分类号： H01L21/336 , H01L21/02 , H01L27/06 , H01L29/792 , H01L21/28 , H01L29/51
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513
摘要： A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.
摘要翻译：形成p沟道闪速存储器，其中嵌入有形成有升高的源极/漏极的异质结层中的电荷存储堆叠。实施例包括在衬底上形成虚拟栅极堆叠，通过选择性外延生长在虚设栅极堆叠的每一侧上在衬底上形成层，在层上形成间隔物，形成升高的源极/漏极，去除虚拟栅极堆叠，形成间隔件之间的空腔，并且在空腔中形成存储器栅极堆叠。不同的实施例包括形成窄带隙材料的层，在间隔物下方的窄带隙层和与其相邻的宽带隙层，或在间隔物下方的宽带隙层，与其相邻的窄带隙层，以及宽带隙层窄带隙层。

40. 发明申请

US20140264228A1 FIN SELECTOR WITH GATED RRAM 有权
标题翻译： FIN选择器与门控RRAM
公开(公告)号：US20140264228A1
公开(公告)日：2014-09-18
申请号：US13795894
申请日：2013-03-12
申请人： Eng Huat TOH , Elgin Quek , Shyu Seng Tan
发明人： Eng Huat TOH , Elgin Quek , Shyu Seng Tan
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/146 , H01L45/1666
摘要： A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.
摘要翻译：公开了一种制造具有门控RRAM的翅片选择器和所产生的装置的方法。实施例包括在半导体衬底上形成底电极层和硬掩模; 蚀刻硬掩模，底电极层和半导体衬底以形成鳍状结构; 分别在所述鳍状结构的第一和第二侧表面上形成第一和第二虚拟栅极堆叠; 在所述第一和第二虚拟栅极堆叠的垂直表面上形成间隔物; 形成围绕所述间隔物的ILD; 去除所述第一和第二伪栅极堆叠，在所述鳍状结构的第一和第二侧上形成第一和第二空腔; 在所述第一和第二腔中的鳍状结构的第一和第二侧表面上分别形成RRAM层; 以及用顶部电极填充第一和第二腔中的每一个。

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