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    • 31. 发明授权
    • Ultrasonic treatment apparatus
    • 超音波治疗仪
    • US08251988B2
    • 2012-08-28
    • US11417356
    • 2006-05-03
    • Hiroyuki Takahashi
    • Hiroyuki Takahashi
    • A61B18/04
    • A61B17/22012A61B17/320068A61B2017/00017A61B2017/00482A61B2017/00973
    • An ultrasonic treatment apparatus includes an ultrasonic instrument, a fluid irrigation unit, a fluid suction unit, an ultrasonic driving control unit, and an irrigation/suction control unit. The ultrasonic instrument treats a living-body tissue through ultrasonic vibrations. The fluid irrigation unit supplies a cooling fluid for cooling the ultrasonic instrument to the ultrasonic instrument. The fluid suction unit sucks a cooling fluid irrigated by the fluid irrigation unit to the ultrasonic instrument. The ultrasonic driving control unit controls the driving of ultrasonic vibrations of the ultrasonic instrument. The irrigation/suction control unit sequentially controls the driving of the fluid irrigation unit and the driving of the fluid suction unit in accordance with the output of the ultrasonic driving control unit.
    • 超声波处理装置包括超声波仪器,流体冲洗单元,流体抽吸单元,超声波驱动控制单元和冲洗/抽吸控制单元。 超声波仪器通过超声波振动来治疗生物体组织。 流体冲洗单元提供用于将超声波仪器冷却到超声仪器的冷却流体。 流体抽吸单元将由流体冲洗单元灌注的冷却流体吸入超声波仪器。 超声波驱动控制单元控制超声波仪器的超声波振动的驱动。 冲洗/抽吸控制单元根据超声波驱动控制单元的输出依次控制流体冲洗单元的驱动和流体抽吸单元的驱动。
    • 35. 发明授权
    • Semiconductor integrated circuit having DRAM word line drivers
    • 具有DRAM字线驱动器的半导体集成电路
    • US08036048B2
    • 2011-10-11
    • US12256653
    • 2008-10-23
    • Hiroyuki TakahashiHidetaka Natsume
    • Hiroyuki TakahashiHidetaka Natsume
    • G11C7/00
    • G11C11/4085G11C5/14G11C8/08G11C11/409G11C11/4091
    • A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.
    • 根据本发明的一个方面的半导体集成电路可以包括多个驱动电路,用于根据第一电源提供的第一电压或从第二电源提供的第二电压驱动相应的多个字线 具有控制信号,以及多个栅极晶体管,其中每个栅极连接到多条字线中的一条字线,并且存储节点和位线之间的连接状态基于提供给字的电压而改变 线连接到门。 在半导体集成电路中,多个栅极晶体管的栅极氧化膜比构成多个驱动电路的晶体管的栅极氧化膜薄。
    • 40. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20110096596A1
    • 2011-04-28
    • US12912309
    • 2010-10-26
    • Hiroyuki TakahashiNaoki Ookuma
    • Hiroyuki TakahashiNaoki Ookuma
    • G11C11/34
    • G11C5/147G11C11/4074G11C11/4094
    • A semiconductor memory device includes: a memory cell array provided with a plurality of memory cells in a matrix; and a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of the plurality of memory cells. The power supply circuit includes: a first intermediate voltage generating circuit configured to generate a first intermediate voltage between the power supply voltage and the ground voltage; a second intermediate voltage generating circuit configured to generate a second intermediate voltage between the power supply voltage and the ground voltage; a first output node to which the first intermediate voltage is supplied; a second output node to which the second intermediate voltage is supplied; and a connection control circuit provided between the first output node and the second output node. The first intermediate voltage generating circuit supplies the first intermediate voltage in response to a first control signal, and the second intermediate voltage generating circuit stops its operation in response to the first control signal. The connection control circuit connects the first output node and the second output node when the second intermediate voltage generating circuit stops its operation.
    • 半导体存储器件包括:以矩阵形式设置有多个存储单元的存储单元阵列; 以及电源电路,被配置为向所述多个存储单元中的每一个提供电源电压和接地电压之间的中间电压。 电源电路包括:第一中间电压产生电路,被配置为在电源电压和接地电压之间产生第一中间电压; 第二中间电压产生电路,被配置为在电源电压和接地电压之间产生第二中间电压; 提供第一中间电压的第一输出节点; 提供第二中间电压的第二输出节点; 以及连接控制电路,设置在第一输出节点和第二输出节点之间。 第一中间电压产生电路响应于第一控制信号提供第一中间电压,并且第二中间电压产生电路响应于第一控制信号停止其操作。 当第二中间电压产生电路停止工作时,连接控制电路连接第一输出节点和第二输出节点。