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31. 发明授权

US07585773B2 Non-conformal stress liner for enhanced MOSFET performance 失效
标题翻译：非保形应力衬垫，用于增强MOSFET性能
公开(公告)号：US07585773B2
公开(公告)日：2009-09-08
申请号：US11556591
申请日：2006-11-03
申请人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
发明人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
IPC分类号： H01L29/72
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.
摘要翻译：提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。本发明是针对制造所述半导体器件的方法。

32. 发明授权

US07482215B2 Self-aligned dual segment liner and method of manufacturing the same 有权
标题翻译：自对准双段衬管及其制造方法
公开(公告)号：US07482215B2
公开(公告)日：2009-01-27
申请号：US11468536
申请日：2006-08-30
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L21/8238 , H01L21/302 , H01L21/461 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/823807 , H01L29/7843
摘要： A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the second liner having a first section covering the first protective layer, a transitional section, and a second section covering the second set of semiconductor devices, the second section being self-aligned to the first liner via the transitional section; forming a second protective layer on top of the second section of the second liner; removing the first section and at least part of the transitional section of the second liner; and obtaining the dual segment liner including the first liner, the transitional section and the second section of the second liner. A semiconductor structure with a self-aligned dual segment liner formed in accordance with one embodiment of the invention is also provided.
摘要翻译：提供一种形成覆盖第一组和第二组半导体器件的双段衬套的方法。该方法包括在其顶部形成第一衬垫和第一保护层，第一衬套覆盖第一组半导体器件; 形成第二衬垫，所述第二衬套具有覆盖所述第一保护层的第一部分，过渡部分和覆盖所述第二组半导体器件的第二部分，所述第二部分经由所述过渡部分自对准到所述第一衬里; 在所述第二衬垫的所述第二部分的顶部上形成第二保护层; 移除所述第二衬套的所述第一部分和所述过渡部分的至少一部分; 并且获得包括第一衬套，第二衬套的过渡部分和第二部分的双段衬管。还提供了根据本发明的一个实施例形成的具有自对准双段衬垫的半导体结构。

33. 发明申请

US20090017586A1 CHANNEL STRESS MODIFICATION BY CAPPED METAL-SEMICONDUCTOR LAYER VOLUME CHANGE 审中-公开
标题翻译：通过金属半导体层的体积变化改变通道应力
公开(公告)号：US20090017586A1
公开(公告)日：2009-01-15
申请号：US11774841
申请日：2007-07-09
申请人： Sunfei Fang , Zhijiong Luo
发明人： Sunfei Fang , Zhijiong Luo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/49 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7845
摘要： A method for fabricating a field effect device, such as a field effect transistor, uses a first metal-semiconductor layer, such as a first metal-silicide layer, adjacent a channel in the field effect device. The first metal-semiconductor layer has a first volume. The first metal-semiconductor layer is capped with a capping layer and processed to form a second metal-semiconductor layer that has a second volume different than the first volume. Due to the presence of the capping layer, the difference in volume between the second volume and the first volume introduces a stress into the channel of the field effect device.
摘要翻译：诸如场效应晶体管的场效应器件的制造方法在场效应器件中使用与沟道相邻的第一金属硅化物层等第一金属半导体层。第一金属半导体层具有第一体积。第一金属半导体层用封盖层封盖并加工成形成具有不同于第一体积的第二体积的第二金属半导体层。由于存在覆盖层，第二体积和第一体积之间的体积差异将引起场效应装置的通道中的应力。

34. 发明申请

US20080179638A1 GAP FILL FOR UNDERLAPPED DUAL STRESS LINERS 审中-公开
标题翻译：用于下压双重应力衬里的GAP填料
公开(公告)号：US20080179638A1
公开(公告)日：2008-07-31
申请号：US11669287
申请日：2007-01-31
申请人： Thomas W. Dyer , Sunfei Fang
发明人： Thomas W. Dyer , Sunfei Fang
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/823425 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A gap fill nitride is formed in an underlapping region between a first semiconductor area with a first stress liner and a second semiconductor area with a second stress liner without plugging other tightly spaced structures. This is achieved by filling the tightly spaced structures with middle-of-line dielectric material such as silicon oxide in both the first and the second semiconductor areas prior to the formation of the gap fill nitride. The combination of the first and second stress liners and the gap fill nitride provides a continuous mobile ion diffusion barrier across the entire surface of a CMOS semiconductor structure.
摘要翻译：在具有第一应力衬垫的第一半导体区域和具有第二应力衬垫的第二半导体区域之间的重叠区域中形成间隙填充氮化物，而不堵塞其他紧密间隔的结构。这是通过在形成间隙填充氮化物之前在第一和第二半导体区域中填充紧密间隔的结构与中间线介电材料（例如氧化硅）来实现的。第一和第二应力衬垫和间隙填充氮化物的组合在CMOS半导体结构的整个表面上提供了连续的移动离子扩散势垒。

35. 发明申请

US20080122003A1 NON-CONFORMAL STRESS LINER FOR ENHANCED MOSFET PERFORMANCE 失效
标题翻译：非稳定应力衬管，用于增强MOSFET性能
公开(公告)号：US20080122003A1
公开(公告)日：2008-05-29
申请号：US11556591
申请日：2006-11-03
申请人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
发明人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
IPC分类号： H01L27/092 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.
摘要翻译：提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。本发明是针对制造所述半导体器件的方法。

36. 发明申请

US20070298572A1 FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE 有权
标题翻译：具有多个和/或多个硅化物的场效应晶体管（FET）
公开(公告)号：US20070298572A1
公开(公告)日：2007-12-27
申请号：US11850076
申请日：2007-09-05
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.
摘要翻译：一种半导体结构及其形成方法。首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

37. 发明申请

US20070278585A1 CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS, AND METHODS FOR FABRICATING THE SAME USING FACETED EPITAXY 失效
标题翻译：具有混合信道方向的CMOS器件，以及使用面向外延制造其的方法
公开(公告)号：US20070278585A1
公开(公告)日：2007-12-06
申请号：US11422443
申请日：2006-06-06
申请人： Thomas W. Dyer , Sunfei Fang , Judson R. Holt
发明人： Thomas W. Dyer , Sunfei Fang , Judson R. Holt
IPC分类号： H01L29/94
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/1037 , H01L29/78 , H01L29/7853
摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a first set of equivalent crystal planes, and the second device region contains a protruding semiconductor structure having multiple intercepting surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, a first field effect transistor (FET) can be formed at the first device region, which comprises a channel that extends along the substantially planar surface of the first device region. A second, complementary FET can be formed at the second device region, while the second, complementary FET comprises a channel that extends along the multiple intercepting surfaces of the protruding semiconductor structure at the second device region.
摘要翻译：本发明涉及包括至少第一和第二器件区域的半导体衬底。第一器件区域具有沿着第一组等效晶面中的一个取向的基本平坦的表面，并且第二器件区域包含具有沿第二不同组的等效晶面取向的多个截止面的突出半导体结构。可以使用这种半导体衬底形成半导体器件结构。具体地，可以在第一器件区域处形成第一场效应晶体管（FET），该第一器件区域包括沿着第一器件区域的基本平坦的表面延伸的沟道。第二互补FET可以形成在第二器件区域，而第二互补FET包括在第二器件区域沿着突出半导体结构的多个截止表面延伸的沟道。

38. 发明申请

US20070194387A1 EXTENDED RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED CONTACT AREA AND METHOD FOR FORMING EXTENDED RAISED SOURCE/DRAIN STRUCTURE 有权
标题翻译：用于增强接触区域的扩展源/排水结构和形成扩展源/排水结构的方法
公开(公告)号：US20070194387A1
公开(公告)日：2007-08-23
申请号：US11307759
申请日：2006-02-21
申请人： Thomas Dyer , Sunfei Fang
发明人： Thomas Dyer , Sunfei Fang
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L21/823814 , H01L21/823418 , H01L21/823425 , H01L21/823475 , H01L21/823871 , H01L29/517 , H01L29/66628 , H01L29/7834
摘要： A semiconductor device comprises a gate electrode stack having sidewalls and a top surface with a gate dielectric layer and the gate electrode, and LDD/LDS regions in the substrate aligned with the stack. Conformal L-shaped etch-stop layers with a thickness from about 50 Å to about 200 Å are formed with a vertical leg on the sidewalls of the stack and a horizontal leg reaching over the LDD/LDS regions next to the stack. RSD regions are formed in contact with the substrate aside from the etch-stop layers. The RSD regions cover the horizontal leg of the etch-stop layer and cover at least a portion of the vertical leg of the etch-stop layer on the sidewall of the gate electrode.
摘要翻译：半导体器件包括具有侧壁的栅极电极堆叠和具有栅极电介质层和栅电极的顶表面，并且衬底中的LDD / LDS区域与堆叠对准。形成厚度为约至约200的保形L形蚀刻停止层，其在堆叠的侧壁上具有垂直支腿，并且在堆叠旁边的LDD / LDS区域上形成水平支线。除了蚀刻停止层之外，RSD区域与基板形成接触。 RSD区域覆盖蚀刻停止层的水平支腿并且覆盖栅电极的侧壁上的蚀刻停止层的垂直支腿的至少一部分。

39. 发明申请

US20060244075A1 FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE 失效
标题翻译：具有多个和/或多个硅化物的场效应晶体管（FET）
公开(公告)号：US20060244075A1
公开(公告)日：2006-11-02
申请号：US10908087
申请日：2005-04-27
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触区域和第二S / D扩展区域。对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

40. 发明申请

US20060084256A1 Method of forming low resistance and reliable via in inter-level dielectric interconnect 有权
标题翻译：在层间电介质互连中形成低电阻和可靠通孔的方法
公开(公告)号：US20060084256A1
公开(公告)日：2006-04-20
申请号：US10965031
申请日：2004-10-14
申请人： Cyril Cabral , Lawrence Clevenger , Timothy Dalton , Patrick DeHaven , Chester Dziobkowski , Sunfei Fang , Terry Spooner , Tsong-Lin Tai , Kwong Wong , Chin-Chao Yang
发明人： Cyril Cabral , Lawrence Clevenger , Timothy Dalton , Patrick DeHaven , Chester Dziobkowski , Sunfei Fang , Terry Spooner , Tsong-Lin Tai , Kwong Wong , Chin-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76888
摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.
摘要翻译：具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

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