专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US09183170B2 Asynchronous bridge 有权
标题翻译：异步桥
公开(公告)号：US09183170B2
公开(公告)日：2015-11-10
申请号：US13617734
申请日：2012-09-14
申请人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
发明人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
IPC分类号： G06F3/00 , G06F13/40
CPC分类号： G06F13/405
摘要： An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.
摘要翻译：异步桥包括传输单元和接收单元。发送单元接收写入有效信号并从主电路输入数据，在写入有效信号的控制下输出写入地址增量，按照写入地址的顺序将输入数据依次存储在存储器单元中，然后顺序输出存储的输入数据，按读取地址指示。接收单元基于写入地址和读取地址接收来自从属电路的准备就绪信号，确定存储器单元是否有效，然后基于该确定输出读取有效信号和输入数据。

32. 发明授权

US09034711B2 LDMOS with two gate stacks having different work functions for improved breakdown voltage 有权
标题翻译： LDMOS具有两个栅极叠层，具有不同的功能，可提高击穿电压
公开(公告)号：US09034711B2
公开(公告)日：2015-05-19
申请号：US13046332
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L21/336 , H01L29/78 , H01L29/423 , H01L29/51 , H01L29/49 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/42364 , H01L29/42368 , H01L29/42372 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层，第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

33. 发明授权

US08896072B2 Channel surface technique for fabrication of FinFET devices 有权
标题翻译：用于制造FinFET器件的通道表面技术
公开(公告)号：US08896072B2
公开(公告)日：2014-11-25
申请号：US13736546
申请日：2013-01-08
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.
摘要翻译： FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或倾斜的侧壁。与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

34. 发明授权

US08889494B2 Finfet 有权
公开(公告)号：US08889494B2
公开(公告)日：2014-11-18
申请号：US12980371
申请日：2010-12-29
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L21/84 , H01L21/00 , H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L29/0847 , H01L29/66795 , H01L29/78603
摘要： A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.
摘要翻译：翅片型晶体管包括在衬底表面上的用于将晶体管的栅极与衬底隔离的介质层。电介质层包括非选择性蚀刻的表面，以产生翅片结构的顶部，其具有减小横跨晶片的高度变化。翅片型晶体管还可以包括至少低于S / D区的反掺杂区域，以减小寄生电容以改善其性能。

35. 发明授权

US08674457B2 Methods to reduce gate contact resistance for AC reff reduction 有权
标题翻译：减少AC降低栅极接触电阻的方法
公开(公告)号：US08674457B2
公开(公告)日：2014-03-18
申请号：US12806354
申请日：2010-08-11
申请人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
发明人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.
摘要翻译：制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。这导致较低的栅极接触电阻并有效降低器件的AC Reff。

36. 发明授权

US08530310B2 Memory cell with improved retention 有权
标题翻译：记忆单元具有改善的保留
公开(公告)号：US08530310B2
公开(公告)日：2013-09-10
申请号：US12650561
申请日：2009-12-31
申请人： Lee Wee Teo , Chunshan Yin , Shyue Seng Tan , Chung Foong Tan , Jae Gon Lee , Elgin Quek , Purakh Raj Verma
发明人： Lee Wee Teo , Chunshan Yin , Shyue Seng Tan , Chung Foong Tan , Jae Gon Lee , Elgin Quek , Purakh Raj Verma
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： B82Y10/00 , H01L21/28273 , H01L27/11521
摘要： A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.
摘要翻译：提出了一种形成装置的方法。提供了具有具有第一和第二相邻表面的特征的基底。器件层形成在特征的第一和第二相邻表面上。第一相邻表面上的器件层的第一部分包括纳米晶体，而第二相邻表面上的器件层的第二部分没有纳米晶体。

37. 发明授权

US08349692B2 Channel surface technique for fabrication of FinFET devices 有权
标题翻译：用于制造FinFET器件的通道表面技术
公开(公告)号：US08349692B2
公开(公告)日：2013-01-08
申请号：US13043323
申请日：2011-03-08
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
IPC分类号： H01L21/336
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.
摘要翻译： FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或倾斜的侧壁。与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

38. 发明申请

US20120228676A1 CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES 有权
标题翻译：用于制造FinFET器件的通道表面技术
公开(公告)号：US20120228676A1
公开(公告)日：2012-09-13
申请号：US13043323
申请日：2011-03-08
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Sanford Chu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.
摘要翻译： FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或成角度的侧壁。与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

39. 发明授权

US08242559B2 Integrated circuit system with a floating dielectric region and method of manufacture thereof 有权
标题翻译：具有浮动电介质区域的集成电路系统及其制造方法
公开(公告)号：US08242559B2
公开(公告)日：2012-08-14
申请号：US12422694
申请日：2009-04-13
申请人： Chunshan Yin , Lee Wee Teo , Chung Foong Tan , Jae Gon Lee
发明人： Chunshan Yin , Lee Wee Teo , Chung Foong Tan , Jae Gon Lee
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66636 , H01L29/0653 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/7847 , H01L29/7848 , H01L29/78603 , H01L29/78621
摘要： A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer.
摘要翻译：一种制造集成电路系统的方法包括：在第一层和第三层之间提供第二层; 在第三层上形成有源器件; 形成第三层以在有源器件下方形成岛状区域; 形成第二层以形成在岛区下方具有底切的浮动第二层; 以及围绕岛区域和浮动第二层沉积第四层。

40. 发明申请

US20120072743A1 Hierarchical Power Management Circuit, Power Management Method Using the Same, and System on Chip Including the Hierarchical Power Management Circuit 有权
标题翻译：分层电源管理电路，使用该电路的电源管理方法，以及包括分层电源管理电路的片上系统
公开(公告)号：US20120072743A1
公开(公告)日：2012-03-22
申请号：US13233841
申请日：2011-09-15
申请人： Jae Gon Lee , Bong Il Park , Moo Kyung Kang
发明人： Jae Gon Lee , Bong Il Park , Moo Kyung Kang
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , Y02D10/171
摘要： A hierarchical power management circuit includes N power management circuits respectively included in N power domains each including at least one intellectual property (IP), wherein N is a natural number greater than one. The i-th (1
摘要翻译：分级电源管理电路包括分别包括在N个电源域中的N个电源管理电路，每个电源域包括至少一个知识产权（IP），其中N是大于1的自然数。来自N个电力管理电路的第i（1

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式