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31. 发明申请

US20100306489A1 ERROR MANAGEMENT FIREWALL IN A MULTIPROCESSOR COMPUTER 有权
标题翻译：多处理器计算机中的错误管理防火墙
公开(公告)号：US20100306489A1
公开(公告)日：2010-12-02
申请号：US12474556
申请日：2009-05-29
申请人： Dennis C. Abts , Steven L. Scott , Aaron F. Godfrey
发明人： Dennis C. Abts , Steven L. Scott , Aaron F. Godfrey
IPC分类号： G06F12/14 , G06F15/76 , G06F9/02
CPC分类号： G06F12/1483 , G06F11/0724 , G06F11/0772 , G06F21/52 , H04L1/0045 , H04L63/0227
摘要： A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising a part of one or more of the nodes is operable to prevent a write from an unauthorized processor from writing to the local memory.
摘要翻译：多处理器计算机系统包括多个处理器和多个节点，每个节点包括一个或多个处理器。多个节点中的每一个节点中的本地存储器耦合到每个节点中的处理器，并且包括一个或多个节点的一部分的硬件防火墙可操作以防止来自未授权处理器的写入到本地存储器的写入。

32. 发明授权

US07830905B2 Speculative forwarding in a high-radix router 有权
标题翻译：高基数路由器中的推测转发
公开(公告)号：US07830905B2
公开(公告)日：2010-11-09
申请号：US12107036
申请日：2008-04-21
申请人： Steven L. Scott , Gregory Hubbard , Kelly Marquardt , Roger A. Bethard , Dennis C. Abts
发明人： Steven L. Scott , Gregory Hubbard , Kelly Marquardt , Roger A. Bethard , Dennis C. Abts
IPC分类号： H04L12/56
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： A system and method for speculative forwarding of packets received by a router, wherein each packet includes phits and wherein one or more phits include a cyclic redundancy code (CRC). A packet is received and phits of the packet are forwarded to router logic. A cyclic redundancy code for the packet is calculated and compared to the packet's cyclic redundancy code. An error is generated if the cyclic redundancy codes don't match. If the cyclic redundancy codes don't match, a phit of the packet is modified to reflect the error, the CRC is corrected and the corrected CRC is forwarded to the router logic along with the phit reflecting the CRC error. At the router logic, a check is made to see if the packet is still within the router logic. If the packet is still within the router logic and there was a CRC error, the packet is discarded. If, however, the packet is no longer within the router logic and there was a CRC error, the packet is modified so that the next router discards the packet.
摘要翻译：一种用于对由路由器接收的分组进行推测转发的系统和方法，其中每个分组包括点对点，并且其中一个或多个点包括循环冗余码（CRC）。接收到一个数据包，并将数据包的phits转发给路由器逻辑。计算分组的循环冗余码，并将其与分组的循环冗余码进行比较。如果循环冗余码不匹配，则会产生错误。如果循环冗余码不匹配，则修改该分组的phit以反映该错误，校正CRC并将校正的CRC与反映CRC错误的phit一起转发到路由器逻辑。在路由器逻辑上，检查数据包是否仍在路由器逻辑内。如果分组仍然在路由器逻辑中，并且出现CRC错误，则丢弃该分组。然而，如果分组不再在路由器逻辑中，并且存在CRC错误，则修改分组，使得下一个路由器丢弃该分组。

33. 发明申请

US20090106529A1 FLATTENED BUTTERFLY PROCESSOR INTERCONNECT NETWORK 有权
标题翻译：扁平化处理器互连网络
公开(公告)号：US20090106529A1
公开(公告)日：2009-04-23
申请号：US12195190
申请日：2008-08-20
申请人： Dennis C. Abts , John Kim , William J. Dally
发明人： Dennis C. Abts , John Kim , William J. Dally
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/17375
摘要： A multiprocessor computer system comprises a folded butterfly processor interconnect network, the folded butterfly interconnect network comprising a traditional butterfly interconnect network derived from a butterfly network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.
摘要翻译：多处理器计算机系统包括折叠蝶形处理器互连网络，折叠蝶形互连网络包括通过将每行中的路由器平坦化为每行的单个路由器，并且消除完全局部于单个路由的通道，从蝴蝶网络衍生的传统蝶形互连网络行。

34. 发明授权

US08761166B2 Flexible routing tables for a high-radix router 有权
标题翻译：高基数路由器的灵活路由表
公开(公告)号：US08761166B2
公开(公告)日：2014-06-24
申请号：US12942483
申请日：2010-11-09
申请人： Steven L. Scott , Gregory Hubbard , Dennis C. Abts
发明人： Steven L. Scott , Gregory Hubbard , Dennis C. Abts
IPC分类号： H04L12/28
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.
摘要翻译：用于在高基数网络中路由的系统和方法。接收并检查分组以确定分组是否可以自适应路由。如果分组可以自适应地路由，则分组自适应路由，其中路由自适应地包括选择列，计算列掩码，将分组路由到列; 并根据列屏蔽选择输出端口。如果分组可以确定地路由路由，确定性地进行路由，其中路由确定性地包括访问路由表以获得输出端口并且将路由从路由表路由到输出端口。

35. 发明授权

US08601297B1 Systems and methods for energy proportional multiprocessor networks 有权
标题翻译：能量比例多处理器网络的系统和方法
公开(公告)号：US08601297B1
公开(公告)日：2013-12-03
申请号：US12818580
申请日：2010-06-18
申请人： Dennis C. Abts , Peter Michael Klausler , Hong Liu , Michael Marty , Philip Wells
发明人： Dennis C. Abts , Peter Michael Klausler , Hong Liu , Michael Marty , Philip Wells
IPC分类号： G06F1/32
CPC分类号： G06F1/3253 , H04L41/0833 , H04L43/0882 , H04L69/14 , Y02D10/151 , Y02D50/30
摘要： Energy proportional solutions are provided for computer networks such as datacenters. Congestion sensing heuristics are used to adaptively route traffic across links. Traffic intensity is sensed and links are dynamically activated as they are needed. As the offered load is decreased, the lower channel utilization is sensed and the link speed is reduced to save power. Flattened butterfly topologies can be used in a further power saving approach. Switch mechanisms are exploit the topology's capabilities by reconfiguring link speeds on-the-fly to match bandwidth and power with the traffic demand. For instance, the system may estimate the future bandwidth needs of each link and reconfigure its data rate to meet those requirements while consuming less power. In one configuration, a mechanism is provided where the switch tracks the utilization of each of its links over an epoch, and then makes an adjustment at the end of the epoch.
摘要翻译：为诸如数据中心的计算机网络提供能量比例解决方案。拥塞感知启发式用于自适应地跨链路路由流量。检测到交通强度，并根据需要动态激活链路。随着提供的负载减小，感测到较低的信道利用率，并且减少链路速度以节省功率。扁平蝶形拓扑可以用于进一步节能方法。交换机制通过重新配置链路速度来快速利用拓扑的功能，以匹配带宽和功率与流量需求。例如，系统可以估计每个链路的未来带宽需求，并重新配置其数据速率以满足这些要求，同时消耗更少的功率。在一种配置中，提供了一种机制，其中开关在历元上跟踪其每个链接的利用率，然后在时代结束时进行调整。

36. 发明授权

US08407167B1 Method for optimizing memory controller configuration in multi-core processors using fitness metrics and channel loads 有权
标题翻译：使用健身度量和信道负载优化多核处理器中的存储器控制器配置的方法
公开(公告)号：US08407167B1
公开(公告)日：2013-03-26
申请号：US12487957
申请日：2009-06-19
申请人： Dennis C. Abts , Daniel Gibson
发明人： Dennis C. Abts , Daniel Gibson
IPC分类号： G06F15/18
CPC分类号： G06F12/0813 , G06F15/17312 , G06F17/5072 , G06F17/5077
摘要： The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network.
摘要翻译：多处理器架构的片上架构内的存储器控制器的位置在处理器到存储器流量的延迟带宽特性中起着核心作用。根据所选择的特定内存控制器配置，智能放置可显着降低最大通道负载。各种模拟技术沿着并结合使用以确定最佳的存储器控制器布置。在多处理器阵列中跨所有行和列传播网络流量的钻石型和对角X型存储器控制器配置大大改进了其他布置。这样的布局将实际工作负载的互连延迟平均降低了10％，而相对于片上内核数量的少量内存控制器开辟了丰富的设计空间，以优化片上网络的延迟和带宽特性。

37. 发明授权

US08239704B2 Global clock via embedded spanning tree 有权
标题翻译：全球时钟通过嵌入式生成树
公开(公告)号：US08239704B2
公开(公告)日：2012-08-07
申请号：US12483886
申请日：2009-06-12
申请人： Steven L. Scott , Dennis C. Abts , Aaron F. Godfrey
发明人： Steven L. Scott , Dennis C. Abts , Aaron F. Godfrey
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： In some embodiments, the present invention relates to a method of maintaining a global clock within a multiprocessor system having a plurality of nodes that are connected in a network via links. A virtual spanning tree is mapped onto the network and the nodes and the links are configured such that each node is in a parent-child relationship with one or more other nodes in the virtual spanning tree. A global clock is generated in a root of the virtual spanning tree and global clock signals are communicated down the virtual spanning tree to each of the nodes.
摘要翻译：在一些实施例中，本发明涉及一种在多处理器系统内维护全局时钟的方法，该多处理器系统具有通过链路连接在网络中的多个节点。虚拟生成树被映射到网络上，并且配置节点和链路，使得每个节点与虚拟生成树中的一个或多个其他节点处于父子关系。在虚拟生成树的根中生成全局时钟，并将全局时钟信号从虚拟生成树传送到每个节点。

38. 发明申请

US20100318774A1 PROCESSOR INSTRUCTION GRADUATION TIMEOUT 审中-公开
标题翻译：加工商指导评估超时
公开(公告)号：US20100318774A1
公开(公告)日：2010-12-16
申请号：US12483902
申请日：2009-06-12
申请人： Dennis C. Abts , Aaron F. Godfrey
发明人： Dennis C. Abts , Aaron F. Godfrey
IPC分类号： G06F9/38 , G06F11/07
CPC分类号： G06F11/0793 , G06F9/30087 , G06F9/3861 , G06F11/0721 , G06F11/0724 , G06F11/0757
摘要： A multiprocessor computer system comprises a plurality of processors distributed across a plurality of node coupled by a processor interconnect network. One or more of the processors is operable to manage hung processor instructions by setting a graduation timeout counter after a first program instruction graduates, resetting the graduation timeout counter if a subsequent program instruction graduates before the graduation timeout counter expires, and resetting the processor if the graduation timeout counter expires before the subsequent program instruction graduates.
摘要翻译：多处理器计算机系统包括分布在由处理器互连网络耦合的多个节点上的多个处理器。一个或多个处理器可操作以通过在第一程序指令毕业后设置分度超时计数器来管理挂起的处理器指令，如果后续程序指令在毕业超时计数器到期之前毕业，则重新设置毕业超时计数器，并且如果毕业超时计数器在随后的程序指令毕业之前到期。

39. 发明申请

US20100318626A1 EXTENDED FAST MEMORY ACCESS IN A MULTIPROCESSOR COMPUTER SYSTEM 有权
标题翻译：在多处理器计算机系统中扩展的快速存储器访问
公开(公告)号：US20100318626A1
公开(公告)日：2010-12-16
申请号：US12483936
申请日：2009-06-12
申请人： Dennis C. Abts , Robert Alverson , Edwin Froese , Howard Pritchard , Steven L. Scott
发明人： Dennis C. Abts , Robert Alverson , Edwin Froese , Howard Pritchard , Steven L. Scott
IPC分类号： G06F15/167 , G06F12/00 , G06F12/08
CPC分类号： G06F15/167 , G06F9/3834 , G06F12/0813 , G06F12/1009 , G06F12/109 , G06F13/4009 , G06F2212/163 , H04L67/00
摘要： A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.
摘要翻译：多处理器计算机系统包括第一节点，用于通过从第一节点中的节点逻辑中的请求实体接收虚拟存储器地址来访问远程节点本地的存储器。第一节点从节点逻辑中接收的虚拟地址创建网络地址，其中网络地址处于比虚拟存储器地址更大的地址空间中，并且将快速存储器访问请求从第一节点发送到在网络地址。

40. 发明授权

US07843929B2 Flexible routing tables for a high-radix router 有权
标题翻译：高基数路由器的灵活路由表
公开(公告)号：US07843929B2
公开(公告)日：2010-11-30
申请号：US12107016
申请日：2008-04-21
申请人： Steven L. Scott , Gregory Hubbard , Dennis C. Abts
发明人： Steven L. Scott , Gregory Hubbard , Dennis C. Abts
IPC分类号： H04L12/56
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.
摘要翻译：用于在高基数网络中路由的系统和方法。接收并检查分组以确定分组是否可以自适应路由。如果分组可以自适应地路由，则分组自适应路由，其中路由自适应地包括选择列，计算列掩码，将分组路由到列; 并根据列屏蔽选择输出端口。如果分组可以确定地路由路由，确定性地进行路由，其中路由确定性地包括访问路由表以获得输出端口并且将路由从路由表路由到输出端口。

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