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31. 发明授权

US07102201B2 Strained semiconductor device structures 失效
标题翻译：应变半导体器件结构
公开(公告)号：US07102201B2
公开(公告)日：2006-09-05
申请号：US10892467
申请日：2004-07-15
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/78 , H01L23/485 , H01L29/165 , H01L29/41725 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).
摘要翻译：半导体制造方法和结构，器件和集成电路，其特征在于增强的操作性能。结构通常包括形成在半导体材料的主体中的第一和第二源极/漏极区域以及限定在第一和第二源极/漏极区域之间的主体中的沟道区域。在第一和第二源极/漏极区域中的至少一个中设置有多个插塞，每个插塞由容积扩大的材料形成，该压缩应力向沟道区域传递压缩应力。压缩应变通道区域可能是有用的，例如，用于改善p沟道场效应晶体管（PFET）的操作性能。

32. 发明授权

US06891235B1 FET with T-shaped gate 有权
标题翻译：带T形门的FET
公开(公告)号：US06891235B1
公开(公告)日：2005-05-10
申请号：US09713830
申请日：2000-11-15
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Edward Joseph Nowak
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Edward Joseph Nowak
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/10 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/2807 , H01L21/28114 , H01L21/28123 , H01L29/1045 , H01L29/42376 , H01L29/4966 , H01L29/4991 , H01L29/7833
摘要： An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.
摘要翻译： FET具有T形栅极。 FET具有与T的底部自对准的晕圈扩散，并且与顶部自对准的延伸扩散。因此，光环与延伸植入物分离，这提供了显着的优点。 T形门的顶部和底部可以由两种不同材料的层形成，例如锗和硅。两层被图案化在一起。然后，底层的暴露边缘被选择性地化学反应，并且蚀刻掉反应产物以提供凹口。在另一个实施例中，栅极由单个栅极导体形成。金属沿着侧壁共形沉积，凹陷蚀刻以暴露侧壁的顶部，并且被加热以沿底部形成硅化物。蚀刻硅化物以提供凹口。

33. 发明授权

US06875703B1 Method for forming quadruple density sidewall image transfer (SIT) structures 失效
标题翻译：形成四重密度侧壁图像转印（SIT）结构的方法
公开(公告)号：US06875703B1
公开(公告)日：2005-04-05
申请号：US10760500
申请日：2004-01-20
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell
IPC分类号： H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28132
摘要： A method is provided for forming a quadruple density sidewall image transfer (SIT) structure. Oxide spacers are formed on opposite sidewalls of a first mandrel. The oxide spacers form a second mandrel. Then sidewall spacers are formed on opposite sidewalls of the oxide spacers forming the second mandrel. A pattern of the sidewall spacers is used to form the quadruple density sidewall image transfer (SIT) structure. The method of the invention enables formation of four well-controlled lines for each lithographically minimum pitch dimension.
摘要翻译：提供了一种用于形成四重密度侧壁图像转印（SIT）结构的方法。氧化物间隔件形成在第一心轴的相对侧壁上。氧化物间隔物形成第二心轴。然后，侧壁间隔件形成在形成第二心轴的氧化物间隔件的相对侧壁上。侧壁间隔物的图案用于形成四重密度侧壁图像转印（SIT）结构。本发明的方法能够形成用于每个光刻最小间距尺寸的四个良好控制的线。

34. 发明授权

US07994575B2 Metal-oxide-semiconductor device structures with tailored dopant depth profiles 有权
标题翻译：具有定制掺杂深度分布的金属氧化物半导体器件结构
公开(公告)号：US07994575B2
公开(公告)日：2011-08-09
申请号：US11175582
申请日：2005-07-06
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Larry Alan Nesbit
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/2807 , H01L29/4908
摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.
摘要翻译：一种制造金属氧化物半导体器件结构的方法。该方法包括通过离子注入将掺杂剂物质同时引入覆盖在半导体有源层上的绝缘层和栅电极的半导体有源层中。选择半导体有源层的厚度，栅电极的厚度和掺杂剂物质的动能，使得半导体有源层和绝缘层中的掺杂剂物质的投影范围位于绝缘层内，并且投影栅电极中的掺杂物种类的范围位于栅电极内。结果，半导体有源层和栅电极可以在单个离子注入期间同时掺杂，而不需要另外的注入掩模。

35. 发明授权

US07898045B2 Passive electrically testable acceleration and voltage measurement devices 有权
标题翻译：被动电气可测加速度和电压测量装置
公开(公告)号：US07898045B2
公开(公告)日：2011-03-01
申请号：US12166623
申请日：2008-07-02
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Leah Marie Pfeifer Pastel
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Leah Marie Pfeifer Pastel
IPC分类号： H01L29/84
CPC分类号： G01P15/0802 , B82Y15/00 , G01P15/06 , G01P15/0891 , G01P15/135 , H01H1/0094 , H01H35/14
摘要： Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to the nanotubes.
摘要翻译：加速度和电压测量装置以及制造加速度和电压测量装置的方法。所述加速和电压测量装置包括在第一绝缘层的顶表面上的导电板; 在所述导电板的顶表面上的第二绝缘层，所述板的顶表面暴露在所述第二绝缘层的开口中; 导电纳米管悬挂在开口处，并且与纳米管的导电接触。

36. 发明授权

US07851064B2 Methods and structures for promoting stable synthesis of carbon nanotubes 有权
标题翻译：促进碳纳米管稳定合成的方法和结构
公开(公告)号：US07851064B2
公开(公告)日：2010-12-14
申请号：US12031493
申请日：2008-02-14
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
IPC分类号： B32B9/00
CPC分类号： B82Y30/00 , B82Y10/00 , B82Y40/00 , C01B32/162 , C01B2202/06 , C01B2202/22 , C01B2202/34 , H01J1/3044 , H01J2201/30469 , Y10S977/742 , Y10S977/84 , Y10S977/842 , Y10S977/843 , Y10T428/30
摘要： Methods for synthesizing carbon nanotubes and structures formed thereby, includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access.
摘要翻译：合成碳纳米管和由此形成的结构的方法包括在由第一衬底支撑的多个合成位置上形成碳纳米管，中断纳米管合成，将每个碳纳米管的自由端安装到第二衬底上，以及去除第一衬底。每个碳纳米管被其中一个合成位点封盖，生长反应物可以随时进入。

37. 发明申请

US20080160312A1 METHODS AND STRUCTURES FOR PROMOTING STABLE SYNTHESIS OF CARBON NANOTUBES 有权
标题翻译：促进碳纳米管稳定合成的方法和结构
公开(公告)号：US20080160312A1
公开(公告)日：2008-07-03
申请号：US12031493
申请日：2008-02-14
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Peter H. Mitchell , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Peter H. Mitchell , Larry Alan Nesbit
IPC分类号： B32B9/00
CPC分类号： B82Y30/00 , B82Y10/00 , B82Y40/00 , C01B32/162 , C01B2202/06 , C01B2202/22 , C01B2202/34 , H01J1/3044 , H01J2201/30469 , Y10S977/742 , Y10S977/84 , Y10S977/842 , Y10S977/843 , Y10T428/30
摘要： Methods for synthesizing carbon nanotubes and structures formed thereby. The method includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access. As the carbon nanotubes lengthen during resumed nanotube synthesis, access to the synthesis sites remains unoccluded.
摘要翻译：合成碳纳米管的方法及由此形成的结构。该方法包括在由第一基板支撑的多个合成位置上形成碳纳米管，中断纳米管合成，将每个碳纳米管的自由端安装到第二基板上，以及去除第一基板。每个碳纳米管被其中一个合成位点封盖，生长反应物可以随时进入。由于碳纳米管在恢复纳米管合成过程中延长，所以进入合成位点仍未被排除。

38. 发明授权

US07129097B2 Integrated circuit chip utilizing oriented carbon nanotube conductive layers 失效
公开(公告)号：US07129097B2
公开(公告)日：2006-10-31
申请号：US10901858
申请日：2004-07-29
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell
IPC分类号： H01L21/00
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

39. 发明授权

US07038299B2 Selective synthesis of semiconducting carbon nanotubes 失效
标题翻译：半导体碳纳米管的选择性合成
公开(公告)号：US07038299B2
公开(公告)日：2006-05-02
申请号：US10732951
申请日：2003-12-11
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
IPC分类号： H01L29/12 , H01L29/06 , H01L21/205 , H01L21/64
CPC分类号： H01L51/0512 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B2202/22 , C01B2202/34 , C30B25/02 , C30B29/02 , C30B29/605 , H01L51/0048 , Y10S977/854
摘要： Methods for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on multiple synthesis sites carried by a substrate and structures formed thereby. After an initial growth stage, synthesis sites bearing conducting carbon nanotubes are altered to discontinue synthesis at these specific synthesis sites and, thereby, halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration so that semiconducting carbon nanotubes may be lengthened to a greater length than the conducting carbon nanotubes.
摘要翻译：从由衬底承载的多个合成位点上合成的导电和半导体碳纳米管的随机集合以及由此形成的结构选择半导体碳纳米管的方法。在初始生长阶段之后，改变承载导电碳纳米管的合成位点，以在这些特定合成位点停止合成，从而停止导电碳纳米管的延长。具有半导体碳纳米管的合成位点不受改变的影响，使得半导体碳纳米管可以被延长到比导电碳纳米管更长的长度。

40. 发明授权

US06583462B1 Vertical DRAM having metallic node conductor 有权
标题翻译：具有金属节点导体的垂直DRAM
公开(公告)号：US06583462B1
公开(公告)日：2003-06-24
申请号：US09702338
申请日：2000-10-31
申请人： Toshiharu Furukawa , Rajarao Jammy , Thomas Kanarsky , Jeffrey John Welser , David Vaclav Horak , Steven John Holmes , Mark Charles Hakey
发明人： Toshiharu Furukawa , Rajarao Jammy , Thomas Kanarsky , Jeffrey John Welser , David Vaclav Horak , Steven John Holmes , Mark Charles Hakey
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867
摘要： A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a metallic storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. Preferably, the trench has an aspect ratio of greater than 50. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.
摘要翻译：形成在具有沟槽的衬底中的动态随机存取存储器件。沟槽具有侧壁，顶部，下部和圆周。该装置包括信号存储节点，该信号存储节点包括形成在沟槽下部的金属存储节点导体，并通过节点电介质和节点电介质上方的环形氧化物与侧壁隔离。优选地，沟槽具有大于50的纵横比。掩埋带耦合到存储节点导体并且接触环形氧化物上方的沟槽的侧壁的一部分。形成在掩埋带上的沟槽电介质具有沟槽顶部的电介质厚度。信号传送装置包括：第一扩散区域，其延伸到与所述掩埋带接触的所述沟槽侧壁的所述部分相邻的所述衬底;门绝缘体，其具有形成在所述第一掩埋带的上方的所述沟槽侧壁上的栅绝缘体厚度，绝缘体厚度小于沟槽顶部电介质厚度，以及形成在沟槽顶部电介质并且邻近栅极绝缘体的沟槽内的栅极导体。

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