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31. 发明申请

US20080160752A1 METHOD FOR CHIP TO PACKAGE INTERCONNECT 审中-公开
标题翻译：芯片封装互连的方法
公开(公告)号：US20080160752A1
公开(公告)日：2008-07-03
申请号：US11619384
申请日：2007-01-03
申请人： Lawrence Clevenger , Timothy J. Dalton , Mukta Ghate Farooq , William Francis Landers , Carl Radens , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy J. Dalton , Mukta Ghate Farooq , William Francis Landers , Carl Radens , Chih-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/11428 , H01L2224/1145 , H01L2224/1147 , H01L2224/11616 , H01L2224/1184 , H01L2224/11901 , H01L2224/13007 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04953 , H01L2924/0103 , H01L2224/05099
摘要： A damascene method of forming a C4 element includes forming a last level metal layer on a substrate, forming a TV ILD layer on the last level metal layer, forming a lithographically patterned UBM adhesion layer including one of Ti, TiW, Cr and Cu, forming a mandrel layer over the UBM adhesion layer, lithographically patterning the mandrel layer to form an aperture, depositing a solder layer by one of sputtering, evaporation, physical vapor deposition, solder wave or injection molding in the aperture, planarizing the solder layer by CMP, removing the mandrel layer, reflowing the solder to ball the solder to form a ball interconnect, and joining a second substrate with an I/O pad to the ball interconnect.
摘要翻译：形成C4元件的镶嵌方法包括在基底上形成最后一层金属层，在最后一层金属层上形成TV ILD层，形成包括Ti，TiW，Cr和Cu之一的光刻图案的UBM粘附层，形成在UBM粘合层上方的心轴层，光刻图案化心轴层以形成孔，通过溅射，蒸发，物理气相沉积，焊波或注射成型在孔中沉积焊料层，通过CMP平坦化焊料层，去除心轴层，回流焊料以焊接焊料以形成球互连，并将第二衬底与I / O焊盘接合到球互连。

32. 发明申请

US20080160656A1 ADDRESSABLE HIERARCHICAL METAL WIRE TEST METHODOLOGY 失效
标题翻译：可寻址分层金属线测试方法
公开(公告)号：US20080160656A1
公开(公告)日：2008-07-03
申请号：US11619307
申请日：2007-01-03
申请人： Kaushik Chanda , Lawrence Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Chih-Chao Yang
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R31/2858 , H01L22/14 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.
摘要翻译：一种监测和测试电迁移和时间依赖介电击穿的方法包括形成可寻址布线测试阵列，其包括多个或水平布置的金属布线和多个分段垂直布置的探测布线，执行单行连续性/电阻检查以确定所述金属布线的哪一行是打开的，执行完全蛇形连续性/电阻检查，以及确定短缺陷的位置。

33. 发明授权

US07371461B2 Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics 有权
公开(公告)号：US07371461B2
公开(公告)日：2008-05-13
申请号：US11034480
申请日：2005-01-13
申请人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
发明人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
IPC分类号： B32B9/04 , B32B27/00 , H01L21/31 , H01L21/312 , H01L21/314
CPC分类号： H01L21/0331 , H01L21/76811 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/12576 , Y10T428/12611 , Y10T428/31667 , H01L2924/00
摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

34. 发明申请

US20070158717A1 INTEGRATED CIRCUIT COMB CAPACITOR 有权
标题翻译：集成电路组合电容器
公开(公告)号：US20070158717A1
公开(公告)日：2007-07-12
申请号：US11306746
申请日：2006-01-10
申请人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
发明人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L23/5223 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
摘要翻译：本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

35. 发明授权

US07105445B2 Interconnect structures with encasing cap and methods of making thereof 失效
标题翻译：具有封盖的互连结构及其制造方法
公开(公告)号：US07105445B2
公开(公告)日：2006-09-12
申请号：US11034890
申请日：2005-01-14
申请人： Kwong-Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl J. Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
发明人： Kwong-Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl J. Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
IPC分类号： H01L21/44
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连的方法，其包括在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸，并且在所述互连结构的所述延伸部分上沉积包封盖。

36. 发明授权

US07049209B1 De-fluorination of wafer surface and related structure 有权
标题翻译：晶圆表面脱氟及相关结构
公开(公告)号：US07049209B1
公开(公告)日：2006-05-23
申请号：US10907463
申请日：2005-04-01
申请人： Timothy J. Dalton , Nicholas C. M. Fuller , Kaushik A. Kumar , Catherine Labelle
发明人： Timothy J. Dalton , Nicholas C. M. Fuller , Kaushik A. Kumar , Catherine Labelle
IPC分类号： H01L21/322
CPC分类号： H01L21/31138 , H01L21/02063 , H01L21/3105 , H01L21/76814
摘要： Methods of de-fluorinating a wafer surface after damascene processing and prior to photoresist removal are disclosed, as is a related structure. In one embodiment, the method places the wafer surface in a chamber and exposes the wafer surface to a plasma from a source gas including at least one of nitrogen (N2) and/or hydrogen (H2) at a low power density or ion density. The exposing step removes the chemisorbed and physisorbed fluorine residue present on the wafer surface (and chamber), and improves ultra low dielectric (ULK) interconnect structure robustness and integrity. The exposing step is operative due to the efficacy of hydrogen and nitrogen radicals at removing fluorine-based species and also due to the presence of a minimal amount of ion energy in the plasma. The low power density nitrogen and/or hydrogen-containing plasma process enables negligible ash/adhesion promoter interaction and reduces integration complexity during dual damascene processing of low-k OSG-based materials.
摘要翻译：公开了在镶嵌处理之后和光致抗蚀剂去除之前脱晶晶片表面的方法，如相关结构。在一个实施例中，该方法将晶片表面放置在室中并将晶片表面暴露于来自包括氮（N 2 H 2）和/或氢（H 2 ）。曝光步骤去除晶片表面（和室）上存在的化学吸附和物理吸附的氟残基，并改善超低介电（ULK）互连结构的鲁棒性和完整性。曝光步骤由于氢和氮自由基在除去氟基物质的作用以及由于在等离子体中存在最少量的离子能量而有效。低功率密度氮和/或含氢等离子体方法使得可以忽略灰分/粘附促进剂相互作用，并降低在低k OSG基材料的双镶嵌加工过程中的集成复杂性。

37. 发明授权

US06387754B2 Method of forming an on-chip decoupling capacitor with bottom hardmask 失效
标题翻译：用底部硬掩模形成片上去耦电容器的方法
公开(公告)号：US06387754B2
公开(公告)日：2002-05-14
申请号：US09887381
申请日：2001-06-22
申请人： Timothy J. Dalton , Andrew P. Cowley , Peter A. Emmi , Erdem Kaltalioglu , Vincent J. McGahay
发明人： Timothy J. Dalton , Andrew P. Cowley , Peter A. Emmi , Erdem Kaltalioglu , Vincent J. McGahay
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/32136 , H01L21/32139
摘要： An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.
摘要翻译：片上垂直堆叠的去耦电容器包括形成在电容器电介质和下电极之间的硬掩模膜。用于形成电容器的制造工艺利用了硬掩膜，并且使电容器能够在低k电介质材料上形成。由于硬掩模的存在，在用于形成电容器的蚀刻和剥离工艺期间，底层的低k介电材料的攻击被抑制。低k电介质膜提供了在低k电介质材料中形成的相邻导线之间降低的寄生电容，因此提供了更高的集成度。

38. 发明授权

US06358832B1 Method of forming barrier layers for damascene interconnects 有权
标题翻译：形成大马士革互连的阻挡层的方法
公开(公告)号：US06358832B1
公开(公告)日：2002-03-19
申请号：US09641834
申请日：2000-08-18
申请人： Daniel C. Edelstein , Timothy J. Dalton , John G. Gaudiello , Mahadevaiyer Krishnan , Sandra G. Malhotra , Maurice McGlashan-Powell , Eugene J. O'Sullivan , Carlos J. Sambucetti
发明人： Daniel C. Edelstein , Timothy J. Dalton , John G. Gaudiello , Mahadevaiyer Krishnan , Sandra G. Malhotra , Maurice McGlashan-Powell , Eugene J. O'Sullivan , Carlos J. Sambucetti
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/288 , H01L21/3212 , H01L21/76829 , H01L21/76834 , H01L21/76835
摘要： A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.
摘要翻译：包含双蚀刻停止/扩散屏障的镶嵌互连。镶嵌互连的导电材料用导电金属扩散阻挡盖（通常使用无电沉积）和可选地与电介质蚀刻停止层封盖。还可以存在任选的化学机械抛光 - 停止层。本发明的不同方法允许不同层的CMP停止，反应离子蚀刻停止和金属扩散阻挡层要求被去耦合。优选的导电材料是铜。

39. 发明授权

US5788869A Methodology for in situ etch stop detection and control of plasma etching process and device design to minimize process chamber contamination 失效
标题翻译：用于原位蚀刻停止检测和控制等离子体蚀刻工艺和器件设计的方法，以最小化处理室污染
公开(公告)号：US5788869A
公开(公告)日：1998-08-04
申请号：US552322
申请日：1995-11-02
申请人： Timothy J. Dalton , Ann C. Westerheim , Jamshed Hoshang Dubash , Marion Garver , Richard A. Bickford
发明人： Timothy J. Dalton , Ann C. Westerheim , Jamshed Hoshang Dubash , Marion Garver , Richard A. Bickford
IPC分类号： H01J37/32 , H01L21/66 , H01L21/768
CPC分类号： B24B37/013 , H01J37/32935 , H01J37/32963 , H01L21/76802 , H01L22/26 , H01L2924/0002 , Y10S438/905
摘要： A method of etching a dielectric layer to form a via to an underlying conductive layer is described. The method includes etching selected portions of the dielectric using a plasma containing an etchant and monitoring electromagnetic energy of plasma emission radiation from the species to determine a ratio of a pair of the species in the plasma that is used to indicate the onset of an etch stop phenomenon. Etching of the dielectric continues and additional dielectrics are processed through the plasma etching step while the ratio of species is less than a predetermined threshold value. The process is stopped and a plasma reactor is cleaned once the ratio of the etchants exceeds the threshold value. The method can be used to form vias between a pair of conductive layers. In a preferred approach to form areas for area or bond pads of an integrated circuit during the step of etching the dielectric, the dielectric is masked by a pattern which provides a plurality of vias dispersed within the pad area to be etched forming a sea of contacts or disposed about the periphery of the pad area to be etched forming a ring of contacts contact.
摘要翻译：描述了蚀刻电介质层以形成通孔到底层导电层的方法。该方法包括使用包含蚀刻剂的等离子体蚀刻电介质的选定部分，并监测来自物质的等离子体发射辐射的电磁能，以确定等离子体中用于指示蚀刻停止开始的一对物种的比例现象。电介质的蚀刻继续进行，并且通过等离子体蚀刻步骤处理额外的电介质，而物质的比例小于预定的阈值。一旦蚀刻剂的比例超过阈值，停止该过程并清洁等离子体反应器。该方法可用于在一对导电层之间形成通孔。在蚀刻电介质的步骤期间形成集成电路的区域或接合焊盘的区域的优选方法中，电介质被掩模掩模，该图案提供分散在要蚀刻的焊盘区域内的多个通孔形成接触海或围绕待蚀刻的焊盘区域的周边设置，形成接触环的接触。

40. 发明授权

US08513769B2 Electrical fuses and resistors having sublithographic dimensions 有权
标题翻译：具有亚光刻尺寸的电气保险丝和电阻器
公开(公告)号：US08513769B2
公开(公告)日：2013-08-20
申请号：US12765275
申请日：2010-04-22
申请人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
发明人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
IPC分类号： H01L23/5256 , H01L23/5329 , H01L21/7682
CPC分类号： H01L23/5256 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L27/101 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
摘要翻译：提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。包括导体或半导体的导电结构形成在半导体衬底上。在导电结构上形成至少一个绝缘体层。在所述至少一个绝缘体层中形成凹陷区域。将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

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