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31. 发明申请

US20080132021A1 High Performance FET Devices and Methods Thereof 有权
公开(公告)号：US20080132021A1
公开(公告)日：2008-06-05
申请号：US11971392
申请日：2008-01-09
申请人： Jack Oon Chu
发明人： Jack Oon Chu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/2807 , H01L21/28255 , H01L29/1029 , H01L29/1054 , H01L29/161 , H01L29/41783 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/4966 , H01L29/66628 , H01L29/66795 , H01L29/778 , H01L29/7787 , H01L29/7842 , H01L29/78642 , H01L29/78648 , H01L29/78684 , H01L29/78696
摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

32. 发明申请

US20080124860A1 Metal Gated Ultra Short MOSFET Devices 失效
标题翻译：金属栅极超短MOSFET器件
公开(公告)号：US20080124860A1
公开(公告)日：2008-05-29
申请号：US12013704
申请日：2008-01-14
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

33. 发明授权

US07091095B2 Dual strain-state SiGe layers for microelectronics 有权
标题翻译：用于微电子学的双应变状态SiGe层
公开(公告)号：US07091095B2
公开(公告)日：2006-08-15
申请号：US11053707
申请日：2005-02-08
申请人： Jack Oon Chu
发明人： Jack Oon Chu
IPC分类号： H01L21/336
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02505 , H01L21/02532 , H01L21/02538 , H01L21/76254 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L29/1054
摘要： A strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion is disclosed. The strained crystalline layer is epitaxially bonded, or grown, on top of a SiGe relaxed buffer layer, in a way that the tensilely strained SiGe has a Ge concentration below that of the SiGe relaxed buffer, and the compressively strained SiGe has a Ge concentration above that of the SiGe relaxed buffer. The strained crystalline layer and the relaxed buffer can reside on top a semi-insulator substrate or on top of an insulating divider layer. In some embodiments the tensile SiGe layer is pure Si, and the compressive SiGe layer is pure Ge. The tensilely strained SiGe layer is suited for hosting electron conduction type devices and the compressively strained SiGe is suited for hosting hole conduction type devices. The strained crystalline layer is capable to seed an epitaxial insulator, or a compound semiconductor layer.
摘要翻译：公开了具有拉伸应变SiGe部分和压缩应变SiGe部分的应变结晶层。应变结晶层以SiGe弛豫缓冲层的顶部外延结合或生长，使得拉伸应变SiGe的Ge浓度低于SiGe松弛缓冲液的Ge浓度，并且压缩应变SiGe的Ge浓度高于 SiGe放松缓冲区的那个。应变结晶层和松弛缓冲液可以驻留在半绝缘体衬底上或绝缘分隔层的顶部。在一些实施例中，拉伸SiGe层是纯Si，并且压缩SiGe层是纯Ge。拉伸应变的SiGe层适用于承载电子传导型器件，压缩应变的SiGe适用于承载空穴传导型器件。应变结晶层能够接种外延绝缘体或化合物半导体层。

34. 发明授权

US07067855B2 Semiconductor structure having an abrupt doping profile 失效
标题翻译：具有突变掺杂分布的半导体结构
公开(公告)号：US07067855B2
公开(公告)日：2006-06-27
申请号：US10735167
申请日：2003-12-12
申请人： Frank Cardone , Jack Oon Chu , Khalid EzzEldin Ismail
发明人： Frank Cardone , Jack Oon Chu , Khalid EzzEldin Ismail
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/109 , H01L31/072
CPC分类号： H01L29/36 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/26506 , H01L29/1054 , H01L29/41783 , H01L29/66431 , H01L29/66477 , H01L29/665 , H01L29/66575 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 Å from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET'S, and HBT's.
摘要翻译：描述了形成突变掺杂分布的结构和方法，其结合基板，Ge的第一外延层Ge小于具有大于5×10 19原子/ cc的P或As浓度的临界厚度，以及第二外延层具有大于1×10 19原子/ cc的第一层的第一层的浓度变化。或者，具有Ge含量大于0.5的SiGe层可以相对于分层结构中的其它层选择性地非晶化并重结晶。本发明克服了在诸如CMOS，MODFET和HBT等半导体结构中的Si和SiGe层或膜中形成突变磷分布的问题。

35. 发明申请

US20050161711A1 High performance FET devices and methods thereof 有权
标题翻译：高性能FET器件及其方法
公开(公告)号：US20050161711A1
公开(公告)日：2005-07-28
申请号：US11065816
申请日：2005-02-25
申请人： Jack Oon Chu
发明人： Jack Oon Chu
IPC分类号： H01L21/02 , H01L21/28 , H01L21/336 , H01L27/12 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/778 , H01L29/78 , H01L29/786 , H01L29/04 , H01L31/036
CPC分类号： H01L29/785 , H01L21/2807 , H01L21/28255 , H01L29/1029 , H01L29/1054 , H01L29/161 , H01L29/41783 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/4966 , H01L29/66628 , H01L29/66795 , H01L29/778 , H01L29/7787 , H01L29/7842 , H01L29/78642 , H01L29/78648 , H01L29/78684 , H01L29/78696
摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.
摘要翻译：公开了用于增强的FET器件的制造结构和方法，其中防止掺杂剂杂质通过栅极绝缘体扩散。该结构包括夹在栅极绝缘体和掺杂有杂质的层之间的Si：C或SiGe：C层，以提供预选的功函数。还进一步公开了如何以及对FET器件的进一步改进，诸如凸起源极/漏极和绝缘体上的多面绝缘体，绝缘体上的MODFET与应变的基于Si的绝缘体上的技术集成。

36. 发明授权

US06723621B1 Abrupt delta-like doping in Si and SiGe films by UHV-CVD 失效
标题翻译：通过UHV-CVD在Si和SiGe膜中引起突变的三角形掺杂
公开(公告)号：US06723621B1
公开(公告)日：2004-04-20
申请号：US08885611
申请日：1997-06-30
申请人： Frank Cardone , Jack Oon Chu , Khalid EzzEldin Ismail
发明人： Frank Cardone , Jack Oon Chu , Khalid EzzEldin Ismail
IPC分类号： H01L2120
CPC分类号： H01L29/36 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/26506 , H01L29/1054 , H01L29/41783 , H01L29/66431 , H01L29/66477 , H01L29/665 , H01L29/66575 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 Å from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.
摘要翻译：描述了形成突变掺杂分布的结构和方法，其结合基片，Ge的第一外延层Ge小于P或As浓度大于5×10 19原子/ cc的临界厚度，以及第二外延层，其具有从第一层大于1×10 19 P原子/ cc的第一层的浓度变化。或者，具有Ge含量大于0.5的SiGe层可以相对于分层结构中的其它层选择性地非晶化并重结晶。本发明克服了在诸如CMOS，MODFET和HBT等半导体结构中的Si和SiGe层或膜中形成突变磷分布的问题。

37. 发明授权

US06425951B1 Advance integrated chemical vapor deposition (AICVD) for semiconductor 失效
标题翻译：先进的半导体化学气相沉积（AICVD）技术
公开(公告)号：US06425951B1
公开(公告)日：2002-07-30
申请号：US09369995
申请日：1999-08-06
申请人： Jack Oon Chu , Khalid Ezzeldin Ismail
发明人： Jack Oon Chu , Khalid Ezzeldin Ismail
IPC分类号： C30B3306
CPC分类号： C23C16/54 , C23C16/0209 , C23C16/0227 , C23C16/24 , C30B25/02 , C30B25/08 , Y10S414/138 , Y10S414/139
摘要： An apparatus for forming a portion of an electronic device is described incorporating an Ultra High Vacuum-Chemical Vapor Deposition (UHV-CVD) system, a Low Pressure-Chemical Vapor Deposition (LP-CVD) system, and an Ultra High Vacuum (UHV) transfer system. A method for passivating a semiconductor substrate is described incorporating growing silicon containing layers, flowing a hydrogen containing gas and lowering the substrate temperature below 400° C. A method for removing native oxide is described. A method for growing a continuous epitaxial layer while performing a deposition interrupt is described. A method for forming a Si/Si oxide interface is described having low interface trap density. A method for forming a Si/Si oxide/p++ polysilicon gate stack. The invention overcomes the problem of requiring silicon containing wafers being dipped in HF acid prior to CVD processing. The invention overcomes the problem of surface passivation between in-situ processes in multiple CVD reactors.
摘要翻译：描述了一种用于形成电子器件的一部分的装置，其包括超高真空 - 化学气相沉积（UHV-CVD）系统，低压 - 化学气相沉积（LP-CVD）系统和超高真空（UHV）传输系统。描述了一种用于钝化半导体衬底的方法，其包括生长含硅层，使含氢气体流动并将衬底温度降低到400℃以下。描述了去除天然氧化物的方法。描述了一种在执行沉积中断时生长连续外延层的方法。描述了形成Si / Si氧化物界面的方法具有低界面陷阱密度。一种形成Si / Si氧化物/ p ++多晶硅栅叠层的方法。本发明克服了在CVD处理之前需要将含硅晶片浸入HF酸中的问题。本发明克服了多个CVD反应器中原位过程之间的表面钝化问题。

38. 发明授权

US06251751B1 Bulk and strained silicon on insulator using local selective oxidation 有权
标题翻译：使用局部选择性氧化的绝缘体上的松散和应变硅
公开(公告)号：US06251751B1
公开(公告)日：2001-06-26
申请号：US09290778
申请日：1999-04-13
申请人： Jack Oon Chu , Khalid Ezzeldin Ismail , Kim Yang Lee , John Albrecht Ott
发明人： Jack Oon Chu , Khalid Ezzeldin Ismail , Kim Yang Lee , John Albrecht Ott
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76281
摘要： A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.
摘要翻译：一种用于在单晶半导体层下面形成掩埋氧化物区域的方法，其包括形成具有不同氧化速率的外延层的步骤，下层具有较快的氧化速率和通过掩模中的开口氧化该层。可以形成多个氧化物隔离FET。通过选择性地氧化半导体层，本发明减少了源极/漏极寄生电容和短沟道效应的问题，同时隔离FET并消除FET的浮体效应。

39. 发明授权

US07902012B2 High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof 有权
标题翻译：通过二维带隙工程实现的高速横向异质结MISFET及其方法
公开(公告)号：US07902012B2
公开(公告)日：2011-03-08
申请号：US12534562
申请日：2009-08-03
申请人： Qiqing Christine Ouyang , Jack Oon Chu
发明人： Qiqing Christine Ouyang , Jack Oon Chu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/802 , Y10S438/933
摘要： A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.
摘要翻译：描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变横向沟道结构的方法，其在单晶半导体衬底上结合了漏极，主体和源极区域，其中在晶体管的源极和主体，其中源极区域和沟道独立地相对于身体区域进行晶格应变。本发明通过异质结和晶格应变来减少来自源极区的漏电流的问题，同时通过选择半导体材料和合金组成独立地允许沟道区域中的晶格应变以增加迁移率。

40. 发明授权

US07547930B2 High performance FET devices and methods thereof 有权
标题翻译：高性能FET器件及其方法
公开(公告)号：US07547930B2
公开(公告)日：2009-06-16
申请号：US12013230
申请日：2008-01-11
申请人： Jack Oon Chu
发明人： Jack Oon Chu
IPC分类号： H01L29/745
CPC分类号： H01L29/785 , H01L21/2807 , H01L21/28255 , H01L29/1029 , H01L29/1054 , H01L29/161 , H01L29/41783 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/4966 , H01L29/66628 , H01L29/66795 , H01L29/778 , H01L29/7787 , H01L29/7842 , H01L29/78642 , H01L29/78648 , H01L29/78684 , H01L29/78696
摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected work function. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.
摘要翻译：公开了用于增强的FET器件的制造结构和方法，其中防止掺杂剂杂质通过栅极绝缘体扩散。该结构包括夹在栅极绝缘体和掺杂杂质的层之间的Si：C或SiGe：C层，以提供预选的功函数。还进一步公开了如何以及对FET器件的进一步改进，诸如凸起源极/漏极和绝缘体上的多面绝缘体，绝缘体上的MODFET与应变的基于Si的绝缘体上的技术集成。

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