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31. 发明申请

US20100314767A1 SELF-ALIGNED DUAL DAMASCENE BEOL STRUCTURES WITH PATTERNABLE LOW- K MATERIAL AND METHODS OF FORMING SAME 有权
标题翻译：自对准双DAMASCENE BEOL结构与方形低K材料及其形成方法
公开(公告)号：US20100314767A1
公开(公告)日：2010-12-16
申请号：US12485366
申请日：2009-06-16
申请人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
发明人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/4846 , H01L21/76801 , H01L21/76808 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L23/49894 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.
摘要翻译：提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案）其中。具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。导电材料填充至少一个第一互连图案和至少一个第二互连图案。还提供了形成这种自对准互连结构的方法。

32. 发明申请

US20090072401A1 METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER 失效
标题翻译：使用保护性顶板间隔器减少有机硅电极中的等离子体损伤的方法
公开(公告)号：US20090072401A1
公开(公告)日：2009-03-19
申请号：US11857805
申请日：2007-09-19
申请人： John C. Arnold , Sampath Purushothaman , Muthumanickam Sankarapandian , Hosadurga K. Shobha , Terry A. Spooner
发明人： John C. Arnold , Sampath Purushothaman , Muthumanickam Sankarapandian , Hosadurga K. Shobha , Terry A. Spooner
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5329 , H01L21/76808 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L2924/0002 , H01L2924/00
摘要： Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.
摘要翻译：在形成双镶嵌金属互连结构的超低k电介质材料中的等离子体损伤通过在管线沟槽的侧壁上设置保护隔离物来减少。致密沟槽底部区域可以直接附加地形成在线沟槽的暴露的水平表面下方。保护间隔物和/或致密的沟槽底部区域在用于去除在双镶嵌金属互连结构中使用的一次性通孔填充塞的等离子体条带过程中保护超低k金属间介电层免受等离子体损伤。

33. 发明申请

US20090026625A1 ADHESION ENHANCEMENT FOR METAL/DIELECTRIC INTERFACE 有权
标题翻译：金属/电介质界面的粘合强化
公开(公告)号：US20090026625A1
公开(公告)日：2009-01-29
申请号：US12245133
申请日：2008-10-03
申请人： Chih-Chao Yang , Griselda Bonilla , Qinghuang Lin , Terry A. Spooner
发明人： Chih-Chao Yang , Griselda Bonilla , Qinghuang Lin , Terry A. Spooner
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.
摘要翻译：提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使得被处理的表面变得疏水的处理步骤。在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。

34. 发明申请

US20080173984A1 MECHANICALLY ROBUST METAL/LOW-k INTERCONNECTS 有权
标题翻译：机械稳定的金属/低k互连
公开(公告)号：US20080173984A1
公开(公告)日：2008-07-24
申请号：US11626550
申请日：2007-01-24
申请人： Qinghuang Lin , Terry A. Spooner , Darshan D. Gandhi , Christy S. Tyberg
发明人： Qinghuang Lin , Terry A. Spooner , Darshan D. Gandhi , Christy S. Tyberg
IPC分类号： H01L23/58 , H01L21/31
CPC分类号： H01L21/3105 , H01L21/76805 , H01L21/76825 , H01L21/76826 , H01L21/76834
摘要： A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.
摘要翻译：提供了具有改善的低k电介质层和含电介质衬底之间的粘附强度的机械稳固的半导体结构。特别地，本发明提供了一种结构，其包括含电介质的衬底，其具有包括化学和物理上不同于衬底的经处理的表面层的上部区域; 以及位于所述基板的经处理的表面层上的低k电介质材料。经处理的表面层和低k电介质材料形成界面，该界面的粘合强度大于界面两侧的较弱材料的内聚强度的60％。经处理的表面通过在形成低k电介质材料之前用光化辐射，等离子体和电子束辐射中的至少一种来处理衬底的表面而形成。

35. 发明授权

US07795740B2 Adhesion enhancement for metal/dielectric interface 有权
标题翻译：金属/电介质界面的附着力增强
公开(公告)号：US07795740B2
公开(公告)日：2010-09-14
申请号：US12245133
申请日：2008-10-03
申请人： Chih-Chao Yang , Griselda Bonilla , Qinghuang Lin , Terry A. Spooner
发明人： Chih-Chao Yang , Griselda Bonilla , Qinghuang Lin , Terry A. Spooner
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/53295 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.
摘要翻译：提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使处理后的表面变得疏水的处理步骤。在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。

36. 发明授权

US07781332B2 Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer 失效
标题翻译：使用保护性侧壁间隔物减轻有机硅酸盐电介质中的等离子体损伤的方法
公开(公告)号：US07781332B2
公开(公告)日：2010-08-24
申请号：US11857805
申请日：2007-09-19
申请人： John C. Arnold , Sampath Purushothaman , Muthumanickam Sankarapandian , Hosadurga K. Shobha , Terry A. Spooner
发明人： John C. Arnold , Sampath Purushothaman , Muthumanickam Sankarapandian , Hosadurga K. Shobha , Terry A. Spooner
IPC分类号： H01L21/4763 , H01L21/302
CPC分类号： H01L23/5329 , H01L21/76808 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L2924/0002 , H01L2924/00
摘要： Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.
摘要翻译：在形成双镶嵌金属互连结构的超低k电介质材料中的等离子体损伤通过在管线沟槽的侧壁上设置保护隔离物来减少。致密沟槽底部区域可以直接附加地形成在线沟槽的暴露的水平表面下方。保护间隔物和/或致密的沟槽底部区域在用于去除在双镶嵌金属互连结构中使用的一次性通孔填充塞的等离子体条带过程中保护超低k金属间介电层免受等离子体损伤。

37. 发明申请

US20070273044A1 Adhesion enhancement for metal/dielectric interface 失效
标题翻译：金属/电介质界面的附着力增强
公开(公告)号：US20070273044A1
公开(公告)日：2007-11-29
申请号：US11440984
申请日：2006-05-25
申请人： Chih-Chao Yang , Griselda Bonilla , Qinghuang Lin , Terry A. Spooner
发明人： Chih-Chao Yang , Griselda Bonilla , Qinghuang Lin , Terry A. Spooner
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.
摘要翻译：提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使处理后的表面变得疏水的处理步骤。在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。

38. 发明授权

US07223691B2 Method of forming low resistance and reliable via in inter-level dielectric interconnect 有权
标题翻译：在层间电介质互连中形成低电阻和可靠通孔的方法
公开(公告)号：US07223691B2
公开(公告)日：2007-05-29
申请号：US10965031
申请日：2004-10-14
申请人： Cyril Cabral, Jr. , Lawrence A. Clevenger , Timothy J. Dalton , Patrick W. DeHaven , Chester T. Dziobkowski , Sunfei Fang , Terry A. Spooner , Tsong-Lin L. Tai , Kwong Hon Wong , Chin-Chao Yang
发明人： Cyril Cabral, Jr. , Lawrence A. Clevenger , Timothy J. Dalton , Patrick W. DeHaven , Chester T. Dziobkowski , Sunfei Fang , Terry A. Spooner , Tsong-Lin L. Tai , Kwong Hon Wong , Chin-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76888
摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.
摘要翻译：具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

39. 发明授权

US08519540B2 Self-aligned dual damascene BEOL structures with patternable low- K material and methods of forming same 有权
标题翻译：具有可图案化低K材料的自对准双镶嵌BEOL结构及其形成方法
公开(公告)号：US08519540B2
公开(公告)日：2013-08-27
申请号：US12485366
申请日：2009-06-16
申请人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
发明人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
IPC分类号： H01L23/48
CPC分类号： H01L23/5329 , H01L21/4846 , H01L21/76801 , H01L21/76808 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L23/49894 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.
摘要翻译：提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案）其中。具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。导电材料填充至少一个第一互连图案和至少一个第二互连图案。还提供了形成这种自对准互连结构的方法。

40. 发明申请

US20120231622A1 SELF-ALIGNED DUAL DAMASCENE BEOL STRUCTURES WITH PATTERNABLE LOW- K MATERIAL AND METHODS OF FORMING SAME 有权
标题翻译：自对准双DAMASCENE BEOL结构与方形低K材料及其形成方法
公开(公告)号：US20120231622A1
公开(公告)日：2012-09-13
申请号：US13474349
申请日：2012-05-17
申请人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
发明人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
IPC分类号： H01L21/768
CPC分类号： H01L23/5329 , H01L21/4846 , H01L21/76801 , H01L21/76808 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L23/49894 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.
摘要翻译：提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案）其中。具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。导电材料填充至少一个第一互连图案和至少一个第二互连图案。还提供了形成这种自对准互连结构的方法。

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