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31. 发明申请

US20090216951A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR HANDLING SHARED CACHE LINES IN A MULTI-PROCESSOR ENVIRONMENT 失效
标题翻译：用于在多处理器环境中处理共享缓存行的系统，方法和计算机程序产品
公开(公告)号：US20090216951A1
公开(公告)日：2009-08-27
申请号：US12035668
申请日：2008-02-22
申请人： Chung-Lung Kevin Shum , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/08 , G06F9/30 , G06F9/46
CPC分类号： G06F9/3851 , G06F12/0815
摘要： A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance.
摘要翻译：提供了一种用于处理共享高速缓存行以允许处理器在多处理器环境中的前进进行的系统，方法和计算机程序产品。为多处理器环境的处理器提供计数器和阈值，使得计数器对于跟随指令完成的每个排他交叉询问（XI）拒绝而增加，并且在独占XI确认上复位。如果XI拒绝计数器达到预设阈值，则通过阻止指令发出和预取尝试来消除处理器的流水线，从另一个处理器创建一个独占XI的窗口，从而恢复正常指令处理。将预设阈值配置为可编程值允许微调系统性能。

32. 发明申请

US20090198980A1 FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION 有权
标题翻译：使用更多的排水指令在计算环境中实现加工
公开(公告)号：US20090198980A1
公开(公告)日：2009-08-06
申请号：US12023155
申请日：2008-01-31
申请人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
发明人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3867
摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.
摘要翻译：扩展DRAIN指令用于在计算环境中停止处理。该指令包括处理被停止的一个或多个处理阶段的指示。它还包括一个控制，允许根据需要使处理停滞在额外的周期。

33. 发明申请

US20090182964A1 DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL 有权
标题翻译：动态地址翻译与格式控制
公开(公告)号：US20090182964A1
公开(公告)日：2009-07-16
申请号：US11972706
申请日：2008-01-11
申请人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1009 , G06F2212/1044 , G06F2212/652
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If the format control field is enabled, a frame address of a large block of data in main storage is obtained from the translation table entry. The large block of data is a block of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a desired block of data within the large block of data in main storage. The desired large block of data addressed by the translated address is then accessed.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。虚拟地址的索引部分用于引用转换表中的条目。如果启用格式控制字段，则从转换表条目获得主存储器中的大数据块的帧地址。大块数据是至少1M字节的块。然后将帧地址与虚拟地址的偏移部分组合，以在主存储器中的大量数据块内形成期望的数据块的转换地址。然后访问由翻译的地址寻址的期望的大量数据。

34. 发明申请

US20080168202A1 DIRECTLY INITIATING BY EXTERNAL ADAPTERS THE SETTING OF INTERRUPTION INITIATIVES 有权
标题翻译：通过外部适配器直接启动中断启动的设置
公开(公告)号：US20080168202A1
公开(公告)日：2008-07-10
申请号：US11620141
申请日：2007-01-05
申请人： Douglas G. Balazich , Michael D. Campbell , Janet R. Easton , Mark S. Farrell , Thomas A. Gregg , Kulwant M. Pandey , Gary E. Strait , Charles F. Webb
发明人： Douglas G. Balazich , Michael D. Campbell , Janet R. Easton , Mark S. Farrell , Thomas A. Gregg , Kulwant M. Pandey , Gary E. Strait , Charles F. Webb
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： The setting of interruption initiatives is directly initiated by external adapters. An adapter external to the processors at which the initiative is to be made pending sends a request directly to a system controller coupled to the adapter and the processors. The system controller then broadcasts a command to the processors instructing the processors to set the interruption initiative.
摘要翻译：中断计划的设置由外部适配器直接启动。处理器外部的适配器在外部的适配器将直接发送到耦合到适配器和处理器的系统控制器的请求。然后，系统控制器向指示处理器的处理器广播命令以设置中断主动性。

35. 发明申请

US20080065834A1 Method to Prevent Operand Data with No Locality from Polluting the Data Cache 审中-公开
标题翻译：防止无地点操作数据污染数据缓存的方法
公开(公告)号：US20080065834A1
公开(公告)日：2008-03-13
申请号：US11531288
申请日：2006-09-13
申请人： Mark A. Check , Jennifer A. Navarro , Charles F. Webb
发明人： Mark A. Check , Jennifer A. Navarro , Charles F. Webb
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F9/3832 , G06F12/123 , G06F2212/6028
摘要： A computer system with the means to identify based on the instruction being decoded that the operand data that this instruction will access by its nature will not have locality of access and should be installed in the cache in such a way that each successive line brought into the data cache that hits the same congruence class should be placed in the same set as to not disturb the locality of the data that resided in the cache prior to the execution of the instruction that accessed the data that will not have locality of access.
摘要翻译：一种具有根据正在被解码的指令识别的手段的计算机系统，该指令本身将访问的操作数数据将不具有访问的位置，并且应该以这样的方式安装在每个连续的行中，在同一个集合中的数据高速缓存应放置在相同的集合中，以便在执行访问不具有访问地址的数据的指令之前，不要干扰驻留在缓存中的数据的位置。

36. 发明授权

US06952763B1 Write before read interlock for recovery unit operands 失效
标题翻译：在读取互锁之前写入恢复单元操作数
公开(公告)号：US06952763B1
公开(公告)日：2005-10-04
申请号：US09677363
申请日：2000-10-02
申请人： Scott B. Swaney , Mark S. Farrell , Robert F. Hatch , David P. Hillerud , Charles F. Webb
发明人： Scott B. Swaney , Mark S. Farrell , Robert F. Hatch , David P. Hillerud , Charles F. Webb
IPC分类号： G06F9/30 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3863 , G06F9/3834 , G06F9/3838 , G06F9/3857
摘要： An exemplary embodiment of the invention is a method for holding up recovery unit (R-unit) operands for a minimum number of cycles, until all prior updates have completed, by comparing addresses in at least one queue and interlocking valid R-unit register address matches. The method includes receiving a plurality of R-unit register addresses and storing these R-unit register addresses in at least one queue. This method includes a write queue, a read queue, and a pre-write queue. Further, this method requires accessing these queues and comparing the R-unit register addresses therein. After the addresses are compared, the method determines whether there is a valid match between the R-unit register addresses and if so, implementing one of more interlocks.
摘要翻译：本发明的一个示例性实施例是一种用于通过比较至少一个队列中的地址和互锁的有效R单元寄存器地址来保持最小循环次数的恢复单元（R单元）操作数的方法，直到所有先前更新完成为止火柴。该方法包括接收多个R单元寄存器地址并将这些R单元寄存器地址存储在至少一个队列中。该方法包括写队列，读队列和预写队列。此外，该方法需要访问这些队列并比较其中的R单元寄存器地址。在比较地址之后，该方法确定R单元寄存器地址之间是否存在有效的匹配，如果是，则实现更多的互锁之一。

37. 发明授权

US06751708B2 Method for ensuring that a line is present in an instruction cache 有权
标题翻译：确保指令缓存中存在一行的方法
公开(公告)号：US06751708B2
公开(公告)日：2004-06-15
申请号：US10042534
申请日：2002-01-09
申请人： John S. Liptay , Mark A. Check , Mark S. Farrell , Bruce C. Giamei , Charles F. Webb
发明人： John S. Liptay , Mark A. Check , Mark S. Farrell , Bruce C. Giamei , Charles F. Webb
IPC分类号： G06F1200
CPC分类号： G06F9/3804 , G06F9/30047 , G06F9/30181 , G06F9/3838 , G06F12/0875
摘要： A method is disclosed for instructing a computing system to ensure that a line is present in an instruction cache that includes selecting a line-touch instruction, recognizing the line-touch instruction as a type of branch instruction where the branch is not taken, executing the line-touch instruction to fetch a target line from a target address into the instruction cache, and interlocking the execution of the line-touch instruction with the completion of the fetch of the target line in order to prevent execution of the instruction following the line-touch instruction until after the target line has reached the cache.
摘要翻译：公开了一种用于指示计算系统确保线路存在于指令高速缓存中的方法，所述指令高速缓存包括选择行触摸指令，将线接触指令识别为不采用分支的分支指令的类型，执行线接触指令，用于从目标地址获取目标行到指令高速缓存中，并且将行触摸指令的执行与目标行的获取完成互锁，以防止执行跟踪行指令之后的指令，触摸指令，直到目标行到达缓存。

38. 发明授权

US06560687B1 Method of implementing a translation lookaside buffer with support for a real space control 有权
标题翻译：实现支持实际空间控制的翻译后备缓冲器的方法
公开(公告)号：US06560687B1
公开(公告)日：2003-05-06
申请号：US09677345
申请日：2000-10-02
申请人： Aaron Tsai , Chung-Lung Kevin Shum , Dean G. Bair , Rebecca S. Wisniewski , Charles F. Webb
发明人： Aaron Tsai , Chung-Lung Kevin Shum , Dean G. Bair , Rebecca S. Wisniewski , Charles F. Webb
IPC分类号： G06F1200
CPC分类号： G06F12/1027
摘要： To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer, an existing control bit, the Private Space bit, in the translation lookaside buffer is redefined as an Ignore Common segment bit to create new non-overlapping translation lookaside buffer entries.
摘要翻译：为了支持新的处理器控制位，在具有现有转换后备缓冲器的处理器系统中的实际空间控制（RSC）位将翻译后置缓冲器中的现有控制位，专用空间位重新定义为忽略公共段位创建新的非重叠翻译后备缓冲区条目。

39. 发明授权

US5504859A Data processor with enhanced error recovery 失效
标题翻译：具有增强的错误恢复的数据处理器
公开(公告)号：US5504859A
公开(公告)日：1996-04-02
申请号：US149260
申请日：1993-11-09
申请人： Richard N. Gustafson , John S. Liptay , Charles F. Webb
发明人： Richard N. Gustafson , John S. Liptay , Charles F. Webb
IPC分类号： G06F11/10 , G06F11/14 , G06F11/16
CPC分类号： G06F11/1654 , G06F11/10 , G06F11/1008 , G06F11/1076 , G06F11/1407 , G06F11/1641 , G06F11/165
摘要： Error detection and recovery is provided in a processor of small size and which can be integrated on a single chip by providing buffers for both data and processor status codes in order to contain errors until a subsequent check point preferably generated at the termination of each instruction is reached without detection of an error. Retry of an instruction can therefore be initiated using the status and data validated at the termination of the previous check point and without placing error correction processing in any critical path of the processor. Error detection is accomplished by comparing outputs of at least a pair of unchecked processors for both memory access requests and output data and status codes. Input to the processors is subjected to a parity check and parity check bits are generated for memory access requests. Error correcting codes are generated for data and status codes to allow correction of single bit errors during transmission within the processor or at a storage system. When an error is detected, all data which has not been validated, preferably by changing the logical value of a flag bit associated with each code, at the most recently generated check point is erased. Data codes in which the flag bit has been changed may be transferred to a storage system autonomously even after an error has occurred.
摘要翻译：在小尺寸的处理器中提供错误检测和恢复，并且可以通过为数据和处理器状态代码提供缓冲器来集成在单个芯片上，以便包含错误，直到在每个指令的终止时优选地生成的后续检查点为到达没有检测到错误。因此，可以使用在先前检查点终止时验证的状态和数据来启动指令的重试，并且不在处理器的任何关键路径中进行纠错处理。通过比较两个存储器访问请求和输出数据和状态代码的至少一对未检查处理器的输出来实现错误检测。对处理器的输入进行奇偶校验，并为存储器访问请求生成奇偶校验位。为数据和状态代码生成纠错码，以允许在处理器或存储系统内的传输期间校正单个位错误。当检测到错误时，擦除最近生成的检查点的所有未被验证的数据，优选地通过改变与每个代码相关联的标志位的逻辑值。即使在发生错误之后，标志位已被改变的数据代码也可以被自动地传送到存储系统。

40. 发明申请

US20120144153A1 Dynamic Address Translation With Change Record Override 有权
标题翻译：动态地址转换与更改记录覆盖
公开(公告)号：US20120144153A1
公开(公告)日：2012-06-07
申请号：US13345938
申请日：2012-01-09
申请人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F9/30054 , G06F9/30101 , G06F9/455 , G06F12/1045 , G06F12/109 , G06F12/1475
摘要： A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.
摘要翻译：翻译表条目包含用于控制是否在商店上设置更改位的改变记录覆盖字段。主存储器的每个4K字节块具有包括改变位的相关联的存储密钥。更改记录覆盖字段控制与存储操作的主存储器的期望的4K字节块相关联的存储密钥的改变位是否被设置为1。

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