会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 31. 发明授权
    • Hub and interface for isochronous token ring
    • 集线器和等时令牌环的接口
    • US5687356A
    • 1997-11-11
    • US579555
    • 1995-12-27
    • Claude BassoJean CalvignacFabrice Verplanken
    • Claude BassoJean CalvignacFabrice Verplanken
    • G06F13/00H04L7/00H04L12/433H04L12/64G06F9/00
    • H04L12/6418H04L12/433H04L2012/6437H04L2012/6451H04L2012/6454H04L2012/6459
    • A hub featuring ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous signal streams. The concentration logic comprises clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is comprised of a port transmit interface (44), and a port receive interface (45). Data from a connected station is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) to the next active port, specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to switch (46). The switch and other concentration logic receive a hub local clock (412). Isochronous traffic interchanges with the hub backplane through leads 410 and 411; between ports or between ports and the hub through leads 407 and 409. Data to a connected station is output (408) from port transmit interface (44). Differential Manchester encoded data are received (400) along with Token-Ring clock (401). Control signals are input (403). Isochronous data are received (409). Token-Ring packet Differential Manchester encoded data are finally output from the concentration logic (41).
    • 具有用于将站附接到LAN的端口的集线器包括用于处理复用的进入和输出令牌环和等时信号流的集中逻辑(14)。 浓度逻辑包括来自输入令牌环分组数据流(40)的时钟恢复逻辑(42),用于在输出(400)上再生差分曼彻斯特编码数据,以及恢复令牌环时钟(401)。 周期成帧发生器(43)从集线器背板(402)和令牌环时钟(401)接收125 us同步时钟,并产生到10个端口中的每一个的控制信号(403)。 每个端口由端口传输接口(44)和端口接收接口(45)组成。 来自连接站的数据被输入(404)到端口接收接口(45)。 令牌环包差分曼彻斯特编码数据输出(406)到下一个有效端口,特别是与其恢复的选通时钟(405)一起输出到其端口传输接口,同时将ISO数据输出(407)转换为开关(46)。 交换机和其他集中逻辑接收集线器本地时钟(412)。 通过引线410和411与轮毂底板进行同步通信交换; 通过引线407和409在端口之间或端口之间以及集线器之间。从端口传输接口(44)输出到连接站的数据(408)。 接收差分曼彻斯特编码数据(400)以及令牌环时钟(401)。 控制信号被输入(403)。 接收同步数据(409)。 令牌环包差分曼彻斯特编码数据最终从浓度逻辑输出(41)。
    • 32. 发明授权
    • Data switch
    • 数据开关
    • US06195335B1
    • 2001-02-27
    • US09110917
    • 1998-07-06
    • Jean CalvignacDaniel OrsattiGilles ToubolFabrice VerplankenClaude Basso
    • Jean CalvignacDaniel OrsattiGilles ToubolFabrice VerplankenClaude Basso
    • H04L1256
    • H04L12/5601H04L49/1576H04L2012/5679H04L2012/5681
    • A packet data switch is described comprising a crossbar switch fabric including a set of crosspoint buffers for storing at least one data packet, one for each input/output pair. An input queue is provided for each input-output pair and means are provided for storing incoming data packets in one of the queues corresponding to an input-output routing for the data packet. An input scheduler repeatedly selects one queue from the plurality of queues at each input and a data packet is transferred from the queue selected by the input scheduler from the input queue means to the crosspoint buffer corresponding to the input-output routing for the data packet. A back pressure mechanism is arranged to inhibit selection by the first selector of queues corresponding to input/output pairs for which the respective crosspoint buffer is full. Finally, an output scheduler repeatedly selects for each output one of the crosspoint buffers corresponding to the output and the switch is responsive to the output scheduler to complete the transmission through the switch fabric of the data packet stored in the crosspoint buffer selected by the output scheduler.
    • 描述包数据交换机,其包括交叉开关结构,其包括用于存储至少一个数据分组的一组交叉点缓冲器,每个数据分组一个用于每个输入/输出对。 为每个输入 - 输出对提供输入队列,并且提供装置用于在对应于数据分组的输入 - 输出路由的一个队列中存储输入数据分组。 输入调度器在每个输入处重复从多个队列中选择一个队列,并且将数据分组从输入调度器选择的队列从输入队列装置传送到对应于数据分组的输入 - 输出路由的交叉点缓冲区。 背压机构被布置为禁止第一选择器对应于相应交叉点缓冲器已满的输入/输出对的队列的选择。 最后,输出调度器针对每个输出重复选择对应于输出的交叉点缓冲器之一,并且交换机响应于输出调度器来完成通过存储在由输出调度器选择的交叉点缓冲器中的数据分组的交换结构的传输 。
    • 35. 发明授权
    • Bidirectional packet flow transformation
    • 双向分组流转换
    • US08619782B2
    • 2013-12-31
    • US13325624
    • 2011-12-14
    • Claude BassoJean L CalvignacNatarajan VaidhyanathanFabrice Verplanken
    • Claude BassoJean L CalvignacNatarajan VaidhyanathanFabrice Verplanken
    • H04L12/28H04L12/56G06F7/00G06F17/00
    • H04L29/0653H04L45/50H04L47/2441
    • A network packet includes a packet key that includes one or more source-destination field pairs that each include a source field and a destination field. For each selected source-destination field pair, first and second sections are selected in the packet key. A source field value is extracted from the source field and a destination field value is extracted from the destination field. For each source bit of the source field value: a destination bit is selected from the destination field; an OR logic function is applied to the source bit and the destination bit to generate a first resulting value is stored at the same bit position as the source bit in the first section; an AND logic function is applied to the source bit and the destination bit to generate a second resulting value stored at the same bit position as the source bit in the second section.
    • 网络分组包括分组密钥,其包括一个或多个源 - 目的地字段对,每个源对目的字段对都包括源字段和目的地字段。 对于每个选择的源 - 目的地字段对,在分组密钥中选择第一和第二部分。 从源字段提取源字段值,并从目标字段提取目的字段值。 对于源字段值的每个源位:从目标字段中选择目标位; 将OR逻辑功能应用于源位,并将目标位产生为第一结果值,存储在与第一段中的源位相同的位位置; 将AND逻辑功能应用于源位和目标位,以产生存储在与第二部分中的源位相同的位位置处的第二个结果值。
    • 38. 发明申请
    • CHECKSUM VERIFICATION ACCELERATOR
    • 检查验证加速器
    • US20120151307A1
    • 2012-06-14
    • US13302688
    • 2011-11-22
    • Francois AbelClaude BassoJean L. CalvignacNatarajan VaidhyanathanFabrice Verplanken
    • Francois AbelClaude BassoJean L. CalvignacNatarajan VaidhyanathanFabrice Verplanken
    • G06F11/00
    • H04L1/0079H04L1/0061H04L1/0072
    • Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.
    • 公开了一种用于通过支持第一网络协议和第二网络协议的网络处理器来验证数据分组并利用共享硬件的方法和系统。 网络处理器接收数据包; 识别数据包的网络包协议; 并根据网络分组协议对数据分组进行处理,包括:以第一网络协议特有的第一部分分组长度更新第一寄存器; 用第二网络协议特有的第二部分分组长度更新第二寄存器; 以及用独立于网络协议的字段计算的具有第一校验和的更新第三寄存器。 该系统利用组合来自第一寄存器,第二寄存器和第三寄存器的值的函数产生第二校验和。 系统通过将数据包校验和与第二个校验和进行比较来验证数据包。