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31. 发明授权

US07359275B1 Reduced size dual-port SRAM cell 有权
标题翻译：尺寸减小的双端口SRAM单元
公开(公告)号：US07359275B1
公开(公告)日：2008-04-15
申请号：US11222390
申请日：2005-09-08
申请人： Chau-Chin Wu
发明人： Chau-Chin Wu
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C11/413
摘要： A dual-port Static Random Access Memory (SRAM) cell is disclosed that includes a storage element that is operable to store a data bit and a complement data bit. The dual-port SRAM cell further includes read access circuitry dedicated exclusively to a read operation and write access circuitry dedicated exclusively to a write operation. The read operation and the write operation are performed in a staggered manner. With the read operation performed exclusive on one port and the write operation performed exclusively on the other port of the SRAM cell, smaller transistors can be used to reduce the size of the SRAM cell.
摘要翻译：公开了一种双端口静态随机存取存储器（SRAM）单元，其包括可操作以存储数据位和补码数据位的存储元件。双端口SRAM单元还包括专用于专用于写入操作的读取操作和专用写入访问电路的读取访问电路。读取操作和写入操作以交错方式执行。通过在一个端口上独占执行的读取操作和仅在SRAM单元的另一端口执行的写入操作，可以使用较小的晶体管来减小SRAM单元的尺寸。

32. 发明授权

US06388499B1 Level-shifting signal buffers that support higher voltage power supplies using lower voltage MOS technology 失效
标题翻译：电平移位信号缓冲器，支持使用较低电压MOS技术的高压电源
公开(公告)号：US06388499B1
公开(公告)日：2002-05-14
申请号：US09770099
申请日：2001-01-25
申请人： Ta-Ke Tien , Chau-Chin Wu
发明人： Ta-Ke Tien , Chau-Chin Wu
IPC分类号： H03K190185
CPC分类号： H03K19/00315
摘要： A level-shifting signal buffer contains a totem pole arrangement of MOS transistors connected to an output thereof and a control circuit that drives the totem pole arrangement of MOS transistors in a preferred manner so that none of the signals across the MOS transistors exceed predetermined limits that may damage the MOS transistors. A preferred signal buffer may include a PMOS pull-up transistor and an NMOS pull-down transistor arranged within a transistor totem pole. This transistor totem pole extends between a first power supply signal line that receives a first power supply signal (e.g., Vddext) and a reference signal line that receives a reference signal (e.g., GND). The PMOS pull-up transistor may be configured to support a maximum gate-to-drain voltage which is less than a difference in voltage between the first power supply signal and the reference signal. The control circuit, which is responsive to a data input signal, drives gate electrodes of the PMOS pull-up transistor and the NMOS pull-down transistor with signals that cause an output of the transistor totem pole to swing from a voltage of the first power supply signal line to a voltage of the reference signal line during a pull-down time interval, while simultaneously maintaining a gate-to-drain voltage of the PMOS pull-down transistor within the maximum gate-to-drain voltage throughout the pull-down time interval.
摘要翻译：电平移位信号缓冲器包含连接到其输出的MOS晶体管的图腾柱布置，以及以优选方式驱动MOS晶体管的图腾柱布置的控制电路，使得MOS晶体管两端的信号都不超过预定的限制，可能会损坏MOS晶体管。优选的信号缓冲器可以包括布置在晶体管图腾柱内的PMOS上拉晶体管和NMOS下拉晶体管。该晶体管图腾柱在接收第一电源信号（例如，Vddext）的第一电源信号线和接收参考信号（例如，GND）的参考信号线之间延伸。 PMOS上拉晶体管可以被配置为支持小于第一电源信号和参考信号之间的电压差的最大栅极 - 漏极电压。响应于数据输入信号的控制电路利用引起晶体管图腾柱的输出从第一功率的电压摆动的信号驱动PMOS上拉晶体管和NMOS下拉晶体管的栅极电极在下拉时间间隔期间将信号线提供给参考信号线的电压，同时在下拉时同时将PMOS下拉晶体管的栅极至漏极电压保持在最大栅极至漏极电压内时间间隔。

33. 发明授权

US5994945A Circuit for compensating for variations in both temperature and supply voltage 失效
标题翻译：用于补偿温度和电源电压变化的电路
公开(公告)号：US5994945A
公开(公告)日：1999-11-30
申请号：US40329
申请日：1998-03-16
申请人： Chau-Chin Wu , Ta-Ke Tien , Kuo-Huei Yen
发明人： Chau-Chin Wu , Ta-Ke Tien , Kuo-Huei Yen
IPC分类号： H03K19/003 , H03K17/14
CPC分类号： H03K19/00384
摘要： A compensation circuit which accounts for variations in both temperature and V.sub.CC supply voltage on an integrated circuit. The compensation circuit includes four quasi-independent compensation current sources, each of which generates a corresponding compensation current. The first compensation current source generates a first compensation current which has a positive slope with respect to temperature. The second compensation current source generates a second compensation current which has a negative slope with respect to temperature. The third compensation current source generates a third compensation current which has a negative slope with respect to the V.sub.CC supply voltage. The fourth compensation current source generates a fourth compensation current which has a positive slope with respect to the V.sub.CC supply voltage. The first, second, third and fourth compensation currents are summed to create a total compensation current. The compensation current sources are designed to provide different, pre-determined total compensation currents for different temperatures and supply voltages. The predetermined total compensation currents are selected to cause the compensated circuit to transfer signals at a constant speed, regardless of temperature and supply voltage.
摘要翻译：考虑到集成电路的温度和VCC电源电压变化的补偿电路。补偿电路包括四个准独立的补偿电流源，每个补偿电流源产生相应的补偿电流。第一补偿电流源产生相对于温度具有正斜率的第一补偿电流。第二补偿电流源产生相对于温度具有负斜率的第二补偿电流。第三补偿电流源产生相对于VCC电源电压具有负斜率的第三补偿电流。第四补偿电流源产生相对于VCC电源电压具有正斜率的第四补偿电流。将第一，第二，第三和第四补偿电流相加以产生总补偿电流。补偿电流源设计为不同的温度和电源电压提供不同的预定总补偿电流。选择预定的总补偿电流以使补偿电路以恒定速度传送信号，而不管温度和电源电压如何。

34. 发明授权

US06924994B1 Content addressable memory (CAM) devices having scalable multiple match detection circuits therein 失效
标题翻译：内容可寻址存储器（CAM）装置，其中具有可扩展的多重匹配检测电路
公开(公告)号：US06924994B1
公开(公告)日：2005-08-02
申请号：US10385155
申请日：2003-03-10
申请人： James K. Lin , Chau-Chin Wu
发明人： James K. Lin , Chau-Chin Wu
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： Content addressable memory (CAM) devices according to embodiments of the present invention include high performance multiple match detection circuits therein. These match detection circuits use 2-to-1 multiple match gates that are small, consume no static power and are hierarchically cascadable. The match detection circuits are also configured so that match signal inputs see small fanouts and high speed operation can be achieved. At each intermediate and final stage of the match detection circuit, the multiple match gates process two pairs of inputs into a single pair of outputs. In particular, a match detection circuit is configured to generate a final multiple match flag (MMF) and a final any match flag (AMF) in response to input match signals, with the match detection circuit including log2N stages of 2-to-1 multiple match gates, where N=2k and k is a positive integer. The final MMF is set to an active level whenever at least two of the input match signals indicate a match condition and the AMF is set to an active level whenever at least one of the input match signals indicates a match condition.
摘要翻译：根据本发明的实施例的内容可寻址存储器（CAM）设备包括其中的高性能多匹配检测电路。这些匹配检测电路使用较小的2比1多匹配门，不消耗静态功率并且层级级联。匹配检测电路也被配置成使匹配信号输入看到小的扇出，并且可以实现高速操作。在匹配检测电路的每个中间和最后阶段，多个匹配门将两对输入处理成一对输出。特别地，匹配检测电路被配置为响应于输入匹配信号产生最终多重匹配标志（MMF）和最终任意匹配标志（AMF），匹配检测电路包括对数检测电路 N级2对1多个匹配门，其中N = 2K，k是正整数。每当输入匹配信号中的至少两个指示匹配条件并且每当输入匹配信号中的至少一个指示匹配条件时，将AMF设置为有效电平，则最终MMF被设置为有效电平。

35. 发明授权

US6037807A Synchronous sense amplifier with temperature and voltage compensated translator 失效
标题翻译：具有温度和电压补偿转换器的同步读出放大器
公开(公告)号：US6037807A
公开(公告)日：2000-03-14
申请号：US80710
申请日：1998-05-18
申请人： Chau-Chin Wu , Ta-Ke Tien , Wen-Kuan Fang
发明人： Chau-Chin Wu , Ta-Ke Tien , Wen-Kuan Fang
IPC分类号： G11C7/06 , H01L35/00
CPC分类号： G11C7/06
摘要： A bias control circuit for controlling the bias current in a sense amplifier circuit. The bias control circuit maintains a substantially constant bias current when the V.sub.CC supply voltage decreases, thereby maintaining the operating speed of the sense amplifier circuit at a predetermined level. The bias control circuit also increases the bias current as the temperature of the sense amplifier circuit increases, thereby maintaining the operating speed of the sense amplifier circuit at the predetermined level. Furthermore, the bias circuit controls the logic low voltage provided by the sense amplifier circuit to be less than a predetermined threshold value, even as the V.sub.CC supply voltage increases.
摘要翻译：用于控制读出放大器电路中的偏置电流的偏置控制电路。当VCC电源电压降低时，偏置控制电路保持基本恒定的偏置电流，从而将读出放大器电路的工作速度保持在预定的水平。当感测放大器电路的温度升高时，偏置控制电路也增加偏置电流，从而将读出放大器电路的工作速度保持在预定的水平。此外，即使VCC电源电压增加，偏置电路将由读出放大器电路提供的逻辑低电压控制为小于预定阈值。

36. 发明授权

US5483183A Bipolar current sense amplifier 失效
标题翻译：双极电流检测放大器
公开(公告)号：US5483183A
公开(公告)日：1996-01-09
申请号：US194773
申请日：1994-02-10
申请人： Richard C. Li , Chau-Chin Wu , Ta-Ke Tien
发明人： Richard C. Li , Chau-Chin Wu , Ta-Ke Tien
IPC分类号： H03F3/45 , H03K5/24 , G01R19/00
CPC分类号： H03F3/45085 , H03K5/2418 , H03F2203/45352 , H03F2203/45374 , H03F2203/45544 , H03F2203/45564 , H03F2203/45654 , H03F2203/45702
摘要： In a sense amplifier, collectors of a first pair of transistors are connected to and drive the bases of a pair of output transistors, and the bases of the first pair of transistors and the emitters of the pair of output transistors are coupled to input nodes of the sense amplifier. The speed of the sense amplifier is enhanced over the prior art because changes in currents (or voltages) on the input nodes change both the emitter and base voltages of the pair of output transistors.
摘要翻译：在读出放大器中，第一对晶体管的集电极连接到一对输出晶体管的基极并驱动一对输出晶体管的基极，并且第一对晶体管的基极和一对输出晶体管的发射极耦合到读出放大器。由于输入节点上的电流（或电压）的变化改变了一对输出晶体管的发射极和基极电压，所以读出放大器的速度比现有技术增强。

37. 发明授权

US5341333A Circuits and methods for amplification of electrical signals 失效
标题翻译：电信号放大的电路和方法
公开(公告)号：US5341333A
公开(公告)日：1994-08-23
申请号：US929874
申请日：1992-08-11
申请人： Ta-Ke Tien , Chau-Chin Wu
发明人： Ta-Ke Tien , Chau-Chin Wu
IPC分类号： G11C7/06
CPC分类号： G11C7/062
摘要： An amplifier used in some embodiments as a sense amplifier for a memory includes a plurality of first sense amplifiers 220.i whose outputs are connected to high capacitance nodes SA, SA which in turn are connected to inputs of second sense amplifier 240. The state of nodes SA, SA is defined by the currents on the two nodes. The voltages on nodes SA, SA, however, are kept substantially constant, which increases the state switching speed and reduces the power consumption. When the amplifier is not in use and the power-down circuitry reconfigures the amplifier to reduce the power consumption, the second amplifier 240 places its output OUT2 into a valid state in order to prevent oscillations of the output and to reduce power consumption. When the amplifier returns from the power-down mode, the output OUT2 is kept in that state until nodes SA, SA and certain other nodes within the first and second amplifiers settle to proper current and voltage values. As a result, during settling the oscillations on output OUT are prevented and power consumption is reduced.
摘要翻译：在一些实施例中用作存储器的读出放大器的放大器包括多个第一读出放大器220.i，其输出端连接到高电容节点SA，并且上和下连接到第二读出放大器240的输入端。状态节点SA，＆upbar＆S由两个节点上的电流定义。然而，节点SA，＆upbar＆S上的电压保持基本恒定，这增加了状态切换速度并降低了功耗。当放大器未被使用并且掉电电路重新配置放大器以降低功耗时，第二放大器240将其输出OUT2置于有效状态，以便防止输出的振荡并降低功耗。当放大器从掉电模式返回时，输出OUT2保持在该状态，直到第一和第二放大器中的节点SA，上升沿S和某些其他节点达到适当的电流和电压值。结果，在稳定期间，防止输出OUT上的振荡并降低功耗。

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