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31. 发明授权

US07173877B2 Memory system with two clock lines and a memory device 有权
标题翻译：具有两个时钟线和存储器件的存储器系统
公开(公告)号：US07173877B2
公开(公告)日：2007-02-06
申请号：US10955177
申请日：2004-09-30
申请人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.
摘要翻译：本发明涉及一种具有两条时钟线的存储器件的存储器系统。本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回到存储器控制器的读时钟输入。存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。

32. 发明申请

US20070025131A1 Semiconductor memory module and system 失效
标题翻译：半导体存储器模块和系统
公开(公告)号：US20070025131A1
公开(公告)日：2007-02-01
申请号：US11192335
申请日：2005-07-29
申请人： Hermann Ruckerbauer , Simon Muff , Christian Weiss , Peter Gregorius
发明人： Hermann Ruckerbauer , Simon Muff , Christian Weiss , Peter Gregorius
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , G11C5/06 , H05K1/142
摘要： The present invention includes a semiconductor memory modules and semiconductor memory systems using the same. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input linesand the rD signal output lines in a respective point-to-point fashion.
摘要翻译：本发明包括半导体存储器模块和使用其的半导体存储器系统。这些模块将常规DIMM分成一系列独立的较小内存模块。每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。

33. 发明授权

US07050340B1 Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system 有权
标题翻译：半导体存储器系统和用于在半导体存储器系统中传送写和读数据信号的方法
公开(公告)号：US07050340B1
公开(公告)日：2006-05-23
申请号：US10986767
申请日：2004-11-15
申请人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1018
摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.
摘要翻译：用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串具体的突发长度。该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。

34. 发明申请

US20110205828A1 SEMICONDUCTOR MEMORY WITH MEMORY CELL PORTIONS HAVING DIFFERENT ACCESS SPEEDS 失效
标题翻译：具有存储器单元的半导体存储器具有不同的访问速度
公开(公告)号：US20110205828A1
公开(公告)日：2011-08-25
申请号：US12710800
申请日：2010-02-23
申请人： Michael Richter , Markus Balb , Christoph Bilger , Martin Brox , Peter Gregorius , Thomas Hein , Andreas Schneider
发明人： Michael Richter , Markus Balb , Christoph Bilger , Martin Brox , Peter Gregorius , Thomas Hein , Andreas Schneider
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C11/4076 , G11C11/408 , G11C11/4087
摘要： A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.
摘要翻译：一种半导体存储器，包括设置在集成电路上的多个存储体，每个存储体包括存储单元阵列，其中多个存储体的存储单元的第一部分具有第一存取速度和第二部分存储单元多个存储器组具有第二存取速度，其中第一存取速度与第二存取速度不同。

35. 发明授权

US07334150B2 Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals 有权
标题翻译：具有时钟信号再生电路的存储器模块和用于临时存储输入命令和地址信号的寄存器电路
公开(公告)号：US07334150B2
公开(公告)日：2008-02-19
申请号：US11002148
申请日：2004-12-03
申请人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G06F1/04
CPC分类号： G11C5/04 , G11C5/063
摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.
摘要翻译：半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。

36. 发明申请

US20070079057A1 Semiconductor memory system and memory module 审中-公开
标题翻译：半导体存储器系统和存储器模块
公开(公告)号：US20070079057A1
公开(公告)日：2007-04-05
申请号：US11239829
申请日：2005-09-30
申请人： Hermann Ruckerbauer , Peter Gregorius
发明人： Hermann Ruckerbauer , Peter Gregorius
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1673 , G06F13/1684
摘要： A semiconductor memory system is disclosed. In one embodiment, the semiconductor memory system and memory module of the present invention provides a buffer, wherein at least one write buffer chip on the memory module is only buffering and registering write data, command and address signals written from a memory controller to the memory chips. As read data are written back from each memory chip directly to the memory controller through unidirectional point-to-point read data lines the present semiconductor memory system achieves a low latency as compared with a fully buffered DIMM concept. As read data are only unidirectional a high transmission bandwidth can be achieved.
摘要翻译：公开了半导体存储器系统。在一个实施例中，本发明的半导体存储器系统和存储器模块提供了缓冲器，其中存储器模块上的至少一个写入缓冲器芯片仅缓冲并将从存储器控制器写入的写数据，命令和地址信号注册到存储器筹码由于读取数据通过单向点对点读取数据线直接从每个存储器芯片写回存储器控制器，与全缓冲DIMM概念相比，本半导体存储器系统实现了低延迟。由于读取数据只是单向的，所以可以实现高传输带宽。

37. 发明申请

US20060291263A1 Memory system and method of accessing memory chips of a memory system 失效
标题翻译：存储器系统和访问存储器系统的存储器芯片的方法
公开(公告)号：US20060291263A1
公开(公告)日：2006-12-28
申请号：US11128789
申请日：2005-05-13
申请人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
发明人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.
摘要翻译：公开了一种存储器系统和方法。在一个实施例中，存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线被布置在分别指定的拓扑中。连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

38. 发明申请

US20060104132A1 SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR THE TRANSFER OF WRITE AND READ DATA SIGNALS IN A SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：用于半导体存储器系统中写入和读取数据信号的半导体存储器系统和方法
公开(公告)号：US20060104132A1
公开(公告)日：2006-05-18
申请号：US10986767
申请日：2004-11-15
申请人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1018
摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.
摘要翻译：用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串具体的突发长度。该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。

39. 发明授权

US07475187B2 High-speed interface circuit for semiconductor memory chips and memory system including the same 有权
标题翻译：用于半导体存储器芯片的高速接口电路和包含相同的存储器系统
公开(公告)号：US07475187B2
公开(公告)日：2009-01-06
申请号：US11226457
申请日：2005-09-15
申请人： Peter Gregorius , Hermann Ruckerbauer , Paul Wallner
发明人： Peter Gregorius , Hermann Ruckerbauer , Paul Wallner
IPC分类号： G06F15/17
CPC分类号： G11C7/1006 , G11C2207/107 , H03M9/00
摘要： In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path. Optionally the high-speed interface circuit additionally includes a transparent re-driver/transmitter path not including any synchronizing circuitry.
摘要翻译：在半导体存储器系统中，存储器芯片被链接到共享回路前向架构中的存储器模块，并且以点对点连接连接到存储器控制器。每个存储器芯片包括一个高速接口电路，包括：用于重新驱动串行读取数据的读取和写入数据/命令和地址信号重新驱动器/发送器路径，并且写入不预定的数据/命令和地址信号半导体存储芯片; 以及主信号路径，其包括串行到并行转换器和用于串行到并行转换并与参考时钟信号同步的同步器，写入用于半导体存储器芯片的数据/命令和地址信号以及一个并行到串行转换器，用于并行到串行转换从存储器芯片的存储器核心读取的读取数据信号，以及用于将并行到串行转换的读取数据信号插入重新驱动器/发送器路径的开关。可选地，高速接口电路还包括不包括任何同步电路的透明重新驱动器/发射器路径。

40. 发明授权

US07339840B2 Memory system and method of accessing memory chips of a memory system 失效
标题翻译：存储器系统和访问存储器系统的存储器芯片的方法
公开(公告)号：US07339840B2
公开(公告)日：2008-03-04
申请号：US11128789
申请日：2005-05-13
申请人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
发明人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
IPC分类号： G11C7/00
CPC分类号： G11C5/063
摘要： A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.
摘要翻译：讨论了存储器系统和方法。存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线路布置在分别指定的拓扑中。连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

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