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31. 发明授权

US5463322A Method of locating common electrode shorts in an imager assembly 失效
标题翻译：在成像器组件中定位公共电极短路的方法
公开(公告)号：US5463322A
公开(公告)日：1995-10-31
申请号：US161037
申请日：1993-12-03
申请人： Robert F. Kwasnick , Joseph M. Pimbley
发明人： Robert F. Kwasnick , Joseph M. Pimbley
IPC分类号： G09G3/00 , G01R31/08
CPC分类号： G09G3/006
摘要： A process for locating common electrode shorts in an electronic array, such as an x- y- addressed imager assembly having a short circuit between an address line and an overlying common electrode layer, includes the steps of applying a test voltage to the addressed line shorted to the common electrode, measuring current at each of a plurality of common electrode contact points disposed at selected intervals along selected edges of the common electrode, and processing the respective measured currents in accordance with a selected relationship to localize a short circuit location along the length of the shorted address line. In imager assembly arrangements in which it is possible to measure currents on opposite sides of the common electrode disposed substantially perpendicular to the orientation of the shorted address line, the selected relationship is I.sub.A-N /I.sub.a-n =(L-X)/X, wherein: I.sub.A-N are the measured currents from common electrode contact points along one common electrode opposite edge; I.sub.a-n are the measured currents from common electrode contact points along the the other common electrode opposite edge; L represents the length of the shorted address line; and X represents the point of the short circuit as distance from the common electrode first opposite edge. An x- y- addressed imager assembly adapted for use of this method includes a common electrode having more than two electrical contact points disposed at selected intervals along each edge of the common electrode that corresponds to a lateral boundary of the imager assembly.
摘要翻译：用于定位电子阵列中的公共电极短路的方法，例如在地址线和上覆的公共电极层之间具有短路的x-y寻址的成像器组件，包括将测试电压施加到寻址的线路短路在公共电极上测量沿着公共电极的选定边缘以选定间隔设置的多个公共电极接触点中的每一个处的电流，以及根据所选择的关系处理各个测量电流以沿着长度定位短路位置的短路地址线。在成像器组合装置中，其中可以测量基本上垂直于短路地址线的取向设置的公共电极的相对侧上的电流，所选择的关系是IA-N / Ia-n =（LX）/ X，其中：IA-N是沿着一个公共电极相对边缘的公共电极接触点的测量电流; Ia-n是沿着另一个公共电极相对边缘的公共电极接触点的测量电流; L表示短路地址线的长度; X表示作为与公共电极第一相对边缘的距离的短路点。适于使用该方法的x面寻址的成像器组件包括具有多于两个电接触点的公共电极，该电接触点沿着对应于成像器组件的横向边界的公共电极的每个边缘以选定的间隔设置。

32. 发明授权

US5384271A Method for reduction of off-current in thin film transistors 失效
标题翻译：降低薄膜晶体管截止电流的方法
公开(公告)号：US5384271A
公开(公告)日：1995-01-24
申请号：US130807
申请日：1993-10-04
申请人： Robert F. Kwasnick , George E. Possin
发明人： Robert F. Kwasnick , George E. Possin
IPC分类号： H01L21/324 , H01L21/336 , H01L29/78 , H01L29/786 , H01L21/24
CPC分类号： H01L29/66765 , Y10S438/958
摘要： A method of fabricating a thin film transistor having reduced off-current leakage includes the steps of forming a TFT body with a channel region disposed between a source electrode and a drain electrode and then passivating the exposed portion of the channel region. The passivation includes the steps of wet etching the exposed portions of the channel region in an hydrofluoric acid etchant for a first selected etch time; dry etching the exposed channel region in a reactive ion etching procedure for a second selected etch time; wet etching the channel region again with hydrofluoric acid for a third selected etch time; and then treating the channel region with a cleansing agent, such as photoresist stripper; and annealing the exposed portion of the channel region.
摘要翻译：制造具有减少的截止电流泄漏的薄膜晶体管的方法包括以下步骤：形成具有设置在源极和漏极之间的沟道区，然后钝化沟道区的暴露部分的TFT体。钝化包括在第一选择的蚀刻时间内在氢氟酸蚀刻剂中湿蚀刻沟道区的暴露部分的步骤; 在反应离子蚀刻过程中对第二选择的蚀刻时间的暴露的沟道区进行干蚀刻; 用氢氟酸再次湿蚀刻通道区域进行第三选择的蚀刻时间; 然后用清洁剂如光致抗蚀剂剥离剂处理通道区域; 以及对通道区域的暴露部分进行退火。

33. 发明授权

US5362660A Method of making a thin film transistor structure with improved source/drain contacts 失效
标题翻译：制造具有改善的源极/漏极触点的薄膜晶体管结构的方法
公开(公告)号：US5362660A
公开(公告)日：1994-11-08
申请号：US977967
申请日：1992-11-18
申请人： Robert F. Kwasnick , George E. Possin , David E. Holden , Richard J. Saia
发明人： Robert F. Kwasnick , George E. Possin , David E. Holden , Richard J. Saia
IPC分类号： H01L21/3213 , H01L21/336 , H01L29/45 , H01L21/265
CPC分类号： H01L29/66765 , H01L21/32139 , H01L29/458 , Y10S438/97
摘要： Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.
摘要翻译：通过采用具有第一相对薄的第一导体层和第二相对较厚的第二导体层的源极/漏极金属化，薄膜晶体管中的最小线间距减小，并且线间隔均匀性增加。第二导体被选择为可以在第一导体存在的情况下优先蚀刻的导体，由此第一导体充当用于图案化源极/漏极金属化的第二导体部分的蚀刻剂的蚀刻停止。该蚀刻优选使用干蚀刻进行。干蚀刻通常比湿式蚀刻提供对线宽度的更好的控制。第二导体的蚀刻可以通过干法蚀刻工艺进行，该蚀刻工艺以基本上与第二导体相同的速率蚀刻光致抗蚀剂，由此第二导体设置有大致为45°的侧壁斜率，这提高了后续提供的钝化质量共形钝化层的沉积。

34. 发明授权

US07446743B2 Compensating organic light emitting device displays for temperature effects 有权
标题翻译：补偿有机发光器件显示器的温度效应
公开(公告)号：US07446743B2
公开(公告)日：2008-11-04
申请号：US09951834
申请日：2001-09-11
申请人： Robert F. Kwasnick
发明人： Robert F. Kwasnick
IPC分类号： G09G3/30
CPC分类号： G09G3/3208 , G09G2320/0295 , G09G2320/041 , G09G2320/043
摘要： A display may be driven to compensate for the effects of aging on the display. In particular, the temperature of the display may be determined on an ongoing basis and utilized to further correct total integrated charge for temperature effects.
摘要翻译：可以驱动显示器来补偿显示器上的老化的影响。特别地，显示器的温度可以在持续的基础上确定并用于进一步校正温度效应的总积分电荷。

35. 发明申请

US20070300086A1 Processor core wear leveling in a multi-core platform 审中-公开
标题翻译：处理器内核磨损均衡在多核平台上
公开(公告)号：US20070300086A1
公开(公告)日：2007-12-27
申请号：US11476191
申请日：2006-06-27
申请人： Robert F. Kwasnick , Padmashree K. Apparao , Paul F. Newman
发明人： Robert F. Kwasnick , Padmashree K. Apparao , Paul F. Newman
IPC分类号： G06F1/00
CPC分类号： G06F9/5027 , G06F11/008
摘要： A system may comprise a first processor core, a second processor core and a processor core scheduler. The first processor core may include a first circuit to generate a first data and a second processor core may include a second circuit to generate a second data. The processor core scheduler may assign a first thread to the first processor core or to the second processor core based on the first data and the second data.
摘要翻译：系统可以包括第一处理器核心，第二处理器核心和处理器核心调度器。第一处理器核心可以包括产生第一数据的第一电路，而第二处理器核心可以包括产生第二数据的第二电路。处理器核心调度器可以基于第一数据和第二数据将第一线程分配给第一处理器内核或第二处理器内核。

36. 发明授权

US06822256B2 Forming organic light emitting device displays 有权
标题翻译：形成有机发光装置显示
公开(公告)号：US06822256B2
公开(公告)日：2004-11-23
申请号：US09954882
申请日：2001-09-18
申请人： Robert F. Kwasnick , Mary E. Swallow
发明人： Robert F. Kwasnick , Mary E. Swallow
IPC分类号： H01L3300
CPC分类号： H01L51/5253
摘要： An organic light emitting device display may be formed that is suitably passivated while still permitting electrical access to cathodes and anodes via electrical contacts. In one embodiment, a barrier layer may be formed over the light emitting material to prevent moisture or other ambient attack. The barrier layer may be covered with other layers to form an outer and inner via down to the cathode or anode to be contacted. A contact metal may be provided to the anode or cathode. The layers over the barrier layer permit patterning and contact formation while the barrier layer adequately protects the light emitting material during those steps and thereafter.
摘要翻译：可以形成适当钝化的有机发光器件显示器，同时允许通过电触点电接入阴极和阳极。在一个实施例中，阻挡层可以形成在发光材料上方以防止水分或其它环境侵袭。阻挡层可以被其它层覆盖，以形成下接到阴极或阳极的外部和内部通孔。可以向阳极或阴极提供接触金属。阻挡层上方的层允许图案化和接触形成，而阻挡层在这些步骤和之后充分保护发光材料。

37. 发明授权

US5490881A Maintaining uniformity of deposited film thickness in plasma-enhanced chemical vapor deposition 失效
标题翻译：在等离子体增强化学气相沉积中保持沉积膜厚度的均匀性
公开(公告)号：US5490881A
公开(公告)日：1996-02-13
申请号：US970201
申请日：1992-11-02
申请人： Robert F. Kwasnick
发明人： Robert F. Kwasnick
IPC分类号： C23C16/44 , C23C16/458 , C23C16/50
CPC分类号： C23C16/50 , C23C16/44 , C23C16/4585
摘要： In depositing films upon a plate by use of plasma-enhanced chemical vapor deposition, variations in thickness of the film that normally occur at the edges of the plate are reduced by positioning a frame of tiles around the plate. The frame provides a sacrificial edge at which thickness variations at the edge of the film can occur. After deposition, removal of the frame results in improved uniformity of film thickness on the plate itself.
摘要翻译：在通过使用等离子体增强化学气相沉积在薄板上沉积薄膜时，通常在板的边缘处定位一块瓷砖来减少通常在板的边缘处发生的薄膜的厚度变化。该框架提供牺牲边缘，在该牺牲边缘处可能发生胶片边缘处的厚度变化。在沉积之后，移除框架导致板本身上膜厚度的均匀性提高。

38. 发明授权

US5391507A Lift-off fabrication method for self-aligned thin film transistors 失效
标题翻译：自对准薄膜晶体管的剥离制造方法
公开(公告)号：US5391507A
公开(公告)日：1995-02-21
申请号：US115973
申请日：1993-09-03
申请人： Robert F. Kwasnick , George E. Possin
发明人： Robert F. Kwasnick , George E. Possin
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L21/265
CPC分类号： H01L29/78696 , H01L29/66765 , Y10S148/10
摘要： A method of fabricating a self-aligned thin film transistor (TFT) with a lift-off technique includes the steps of forming a multi-tier island on a semiconductive layer such that the island structure is disposed in a desired alignment over the gate electrode. The island structure includes a base layer portion, an intermediate body portion, and an upper cap portion, which overhangs the intermediate body portion by an amount between about 0.5 .mu.m and 1.5 .mu.m. Source and drain electrodes are formed such that the source/drain material is disposed over the semiconductive material up to the sidewalls of the base portion of the island structure, which base portion is patterned such that the source and drain electrodes are self-aligned with and extend a selected overlap distance over the gate to provide desired TFT performance characteristics. The upper cap layer is removed in a lift-off technique and the intermediate body portion of the island is removed to complete fabrication oft the TFT.
摘要翻译：利用剥离技术制造自对准薄膜晶体管（TFT）的方法包括以下步骤：在半导体层上形成多层岛，使得岛状结构以栅极电极的所需对准方式设置。岛结构包括基底层部分，中间体部分和上盖部分，其以约0.5μm和1.5μm之间的量伸出中间体部分。源极和漏极形成为使得源极/漏极材料设置在半导体材料上方直到岛状结构的基部的侧壁，该基极部分被图案化，使得源极和漏极电极自对准，在栅极上延伸选定的重叠距离，以提供所需的TFT性能特征。在剥离技术中去除上盖层，去除岛的中间体部分以完成TFT的制造。

39. 发明授权

US5389775A Imager assembly with multiple common electrode contacts 失效
标题翻译：具有多个公共电极触点的成像仪组件
公开(公告)号：US5389775A
公开(公告)日：1995-02-14
申请号：US161030
申请日：1993-12-03
申请人： Robert F. Kwasnick , Scott W. Petrick , Lawrence R. Skrenes
发明人： Robert F. Kwasnick , Scott W. Petrick , Lawrence R. Skrenes
IPC分类号： H01L27/12 , H01L27/146 , H01L27/14
CPC分类号： H01L27/12 , H01L27/146
摘要： An x-y-addressed imager assembly includes a common electrode having more than two electrical contact points disposed at selected intervals along each edge of the common electrode that corresponds to a lateral boundary of the imager assembly. The selected intervals are typically about equal in length and not greater than about 12% of the length of the edge of the common electrode. The multiple electrical contacts along the common electrode provide low impedance and low magnetic loop area for signals passing along the common electrode to readout and drive circuits.
摘要翻译： x-y寻址的成像器组件包括具有多于两个电接触点的公共电极，该电接触点沿着对应于成像器组件的横向边界的公共电极的每个边缘以选定的间隔设置。所选择的间隔通常在长度上相等并且不大于公共电极边缘的长度的约12％。沿着公共电极的多个电触点为沿着公共电极到读出和驱动电路的信号提供低阻抗和低磁环面积。

40. 发明授权

US5153438A Method of forming an x-ray imaging array and the array 失效
标题翻译：形成X射线成像阵列和阵列的方法
公开(公告)号：US5153438A
公开(公告)日：1992-10-06
申请号：US590846
申请日：1990-10-01
申请人： Jack D. Kingsley , Robert F. Kwasnick
发明人： Jack D. Kingsley , Robert F. Kwasnick
IPC分类号： G01T1/20 , G03B42/02 , G21K4/00
CPC分类号： G21K4/00 , G01T1/2018 , G21K2004/04 , G21K2004/06
摘要： An electronic x-ray imaging array is provided by combining a two-dimensional photosensitive array with a structured scintillator array, having a common array pattern and suitable alignment marks thereon, by bonding them face-to-face in alignment for direct coupling of x-ray luminescence from the scintillator array to the photosensitive array.
摘要翻译：通过将二维光敏阵列与具有共同的阵列图案和适当的对准标记的二维光敏阵列组合在一起，通过将它们面对面地结合在一起来提供x-射线成像阵列，以直接耦合x射线成像阵列，从闪烁体阵列到光敏阵列的射线发光。

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