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31. 发明授权

US5646431A Surface breakdown reduction by counter-doped island in power mosfet 失效
标题翻译：功率mosfet中的反掺杂岛的表面击穿减少
公开(公告)号：US5646431A
公开(公告)日：1997-07-08
申请号：US608385
申请日：1996-02-28
申请人： Ching-Hsiang Hsu , Da-Chi Kuo
发明人： Ching-Hsiang Hsu , Da-Chi Kuo
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66575 , H01L29/0847 , H01L29/66659 , H01L29/7835 , H01L29/0619
摘要： A metal oxide semiconductor field effect transistor with a lightly doped silicon substrate includes an oppositely doped well and oppositely doped source region and oppositely doped drain region with respect to the lightly doped substrate, the improvement comprising at least one counter doped region formed along the surface of the oppositely doped well between the source and drain regions. The substrate comprises a P-substrate, the well comprises an N- well and the counter doped region is doped P; the counterdoped region comprises an island among a plurality of islands between the source region and the drain region. The counterdoped region comprises an island among a plurality of islands between the source region and the drain region.
摘要翻译：具有轻掺杂硅衬底的金属氧化物半导体场效应晶体管包括相对于轻掺杂衬底的相对掺杂的阱和相对掺杂的源极区域和相对掺杂的漏极区域，改进包括至少一个沿着在源极和漏极区之间的相反掺杂阱。衬底包括P衬底，阱包括N阱，并且掺杂的掺杂区被掺杂P; 反向掺杂区域包括在源极区域和漏极区域之间的多个岛状区域中的岛状物。反向掺杂区域包括在源极区域和漏极区域之间的多个岛状区域中的岛状物。

32. 发明授权

US07952934B2 Method for programming a memory structure 有权
标题翻译：用于编程存储器结构的方法
公开(公告)号：US07952934B2
公开(公告)日：2011-05-31
申请号：US12943937
申请日：2010-11-11
申请人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
发明人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
IPC分类号： G11C11/34
CPC分类号： G11C16/3418
摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
摘要翻译：存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。用于对存储器结构进行编程的方法包括：分别向第一存储单元和第二存储单元的栅极提供第一栅极偏置电压和第二栅极偏置电压，提升第一存储单元的沟道电压的绝对值以产生电子和空穴对，通过栅极引起的漏极泄漏或带对带通隧道在第二存储单元的漏极处，并且将所产生的电子和空穴对的空穴注入到第一存储器单元的电荷存储装置中以对第一个存储单元

33. 发明申请

US20110051526A1 METHOD FOR PROGRAMMING A MEMORY STRUCTURE 有权
标题翻译：编程存储器结构的方法
公开(公告)号：US20110051526A1
公开(公告)日：2011-03-03
申请号：US12943937
申请日：2010-11-11
申请人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
发明人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
IPC分类号： G11C16/12 , G11C17/08 , G11C11/40
CPC分类号： G11C16/3418
摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
摘要翻译：存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。用于对存储器结构进行编程的方法包括：分别向第一存储单元和第二存储单元的栅极提供第一栅极偏置电压和第二栅极偏置电压，提升第一存储单元的沟道电压的绝对值以产生电子和空穴对，通过栅极引起的漏极泄漏或带对带通隧道在第二存储单元的漏极处，并且将所产生的电子和空穴对的空穴注入到第一存储器单元的电荷存储装置中以对第一个存储单元

34. 发明申请

US20110031560A1 READ-ONLY MEMORY AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：只读存储器及其制造方法
公开(公告)号：US20110031560A1
公开(公告)日：2011-02-10
申请号：US12536506
申请日：2009-08-06
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Shih-Jye Shen
IPC分类号： H01L27/112 , H01L21/336
CPC分类号： H01L27/112 , G11C17/12 , H01L27/1126
摘要： A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.
摘要翻译：掩模定义的只读存储器阵列形成在衬底上，并且包括具有相反极性的第一ROM位和第二ROM位。第一ROM位具有形成在衬底的第一区域上的第一MOS晶体管和第一阻挡层。第一MOS晶体管的第二源极/漏极区域和第一扩散区域形成在第一块层的相对侧上的衬底的第一区域中。第二ROM位包括第二MOS晶体管。

35. 发明授权

US07855417B2 Non-volatile memory with a stable threshold voltage on SOI substrate 有权
标题翻译：在SOI衬底上具有稳定阈值电压的非易失性存储器
公开(公告)号：US07855417B2
公开(公告)日：2010-12-21
申请号：US11833235
申请日：2007-08-03
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L29/786 , H01L29/792
CPC分类号： H01L27/115
摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the conductive type silicon body layer beneath the gate.
摘要翻译：设置在SOI衬底中的非易失性存储器。非易失性存储器包括存储单元和第一导电类型掺杂区域。存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。栅极设置在SOI衬底上。电荷存储结构设置在栅极和SOI衬底之间。底部电介质层设置在电荷存储层和SOI衬底之间。第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。第一导电型掺杂区域设置在第一导电型硅体层中，并且电连接到栅极下方的导电型硅体层。

36. 发明授权

US07846449B2 Modified mite allergen and pharmaceutical uses thereof 有权
公开(公告)号：US07846449B2
公开(公告)日：2010-12-07
申请号：US11778946
申请日：2007-07-17
申请人： Ching-Hsiang Hsu , Wei-Chih Su
发明人： Ching-Hsiang Hsu , Wei-Chih Su
IPC分类号： A61K39/00 , C07K14/00 , C07K17/00
CPC分类号： A61K39/35 , C07H21/04 , C07K14/43531 , Y10S530/868
摘要： The present invention provides a modified Dermatophagoides pteronyssinus allergen Der p 5 protein which has ability to inhibit IgE binding when exposed against to the antigen. A method for treating allergy comprising administrating a therapeutically effective dose of the modified D. pteronyssinus allergen Der p 5 protein to a subject suffering from allergy Der p 5 is also provided.

37. 发明申请

US20100289834A1 FIELD COLOR SEQUENTIAL DISPLAY CONTROL SYSTEM 审中-公开
标题翻译：现场颜色顺序显示控制系统
公开(公告)号：US20100289834A1
公开(公告)日：2010-11-18
申请号：US12775585
申请日：2010-05-07
申请人： Yung Ching LEE , Ching-Hsiang Hsu
发明人： Yung Ching LEE , Ching-Hsiang Hsu
IPC分类号： G09G5/10
CPC分类号： G09G3/3607 , G09G3/3413 , G09G5/39 , G09G2310/0235 , G09G2360/18
摘要： Field color sequential (FCS) control system applied for an FCS display device is provided. The FCS control system includes an input system, a memory and an output system. The input system, including a plurality of buffers respectively corresponding to different color channels, receives different color channel components of pixels in parallel such that components of a same color channel are stored in a same buffer. The memory, including a plurality of partitions respectively corresponding to different color channels, stores components of a same color channel to a same partition in association with triggering of rising and falling edges of a clock, respectively. The output system sequentially buffers and outputs color channel components of corresponding partitions.
摘要翻译：提供了应用于FCS显示设备的场彩色顺序（FCS）控制系统。 FCS控制系统包括输入系统，存储器和输出系统。包括分别对应于不同颜色通道的多个缓冲器的输入系统并行地接收像素的不同颜色通道分量，使得相同颜色通道的组件被存储在相同的缓冲器中。包括分别对应于不同颜色通道的多个分区的存储器分别将时钟的上升沿和下降沿的触发相关联地存储到相同分区中的相同颜色通道的分量。输出系统顺序地缓冲并输出相应分区的色彩通道分量。

38. 发明申请

US20100259552A1 FIELD COLOR SEQUENTIAL IMAGING METHOD AND RELATED TECHNOLOGY 审中-公开
标题翻译：领域颜色顺序成像方法及相关技术
公开(公告)号：US20100259552A1
公开(公告)日：2010-10-14
申请号：US12757660
申请日：2010-04-09
申请人： Ching-Hsiang Hsu
发明人： Ching-Hsiang Hsu
IPC分类号： G09G5/02
CPC分类号： G09G3/3611 , G09G3/3413 , G09G2310/0235 , G09G2320/0242 , G09G2320/0646
摘要： Field color sequential (FCS) imaging method and technology/apparatus based on FCS principle are provided. In an embodiment, while displaying a frame based on FCS principle, the invention includes: extracting at least a monochrome subfield value and at least a mixed subfield value from each color channel of each pixel of the frame, writing corresponding monochrome subfield value of each pixel in association with a single color channel, and writing corresponding mixed subfield value of each pixel in association with a mixed color which is mixed by at least two color channels.
摘要翻译：提供了基于FCS原理的场彩色顺序（FCS）成像方法和技术/设备。在一个实施例中，在基于FCS原理显示帧的同时，本发明包括：从帧的每个像素的每个颜色通道提取至少一个单色子字段值和至少一个混合子字段值，写入每个像素的相应单色子字段值与单个颜色通道相关联，并且与通过至少两个颜色通道混合的混合颜色相关联地写入每个像素的相应混合子场值。

39. 发明申请

US20090168531A1 METHOD FOR PROGRAMMING A MEMORY STRUCTURE 有权
标题翻译：编程存储器结构的方法
公开(公告)号：US20090168531A1
公开(公告)日：2009-07-02
申请号：US12144645
申请日：2008-06-24
申请人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
发明人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
摘要翻译：存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。一种用于对存储器结构进行编程的方法包括分别向第一存储单元和第二存储单元提供第一栅极偏置电压和第二栅极偏置电压，提高第一存储单元的沟道电压的绝对值以产生电子和空穴通过栅极引起的漏极泄漏或带对带隧穿在第二存储单元的漏极处对，并将所产生的电子和空穴对的电子注入到第一存储单元的电荷存储装置中，以对第一存储单元。

40. 发明授权

US07551494B2 Single-poly non-volatile memory device and its operation method 有权
标题翻译：单聚多边形非易失性存储器件及其操作方法
公开(公告)号：US07551494B2
公开(公告)日：2009-06-23
申请号：US12125912
申请日：2008-05-22
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
IPC分类号： G11C7/00
CPC分类号： G11C16/0475 , G11C16/0466 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/6656 , H01L29/7881 , H01L29/7923
摘要： A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.
摘要翻译：提供了与纳米级半导体制造工艺完全兼容的单聚磷，P沟道非易失性存储单元。单通道P沟道非易失性存储单元包括N阱，形成在N阱上的栅极，栅极和N阱之间的栅极电介质层，栅极侧壁上的ONO层，P +源极掺杂区域和P +漏极掺杂区域。 ONO层包括沉积在栅极的侧壁上并延伸到N阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。氮化硅层用作电荷捕获层。

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