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31. 发明授权

US07470994B2 Bonding pad structure and method for making the same 有权
标题翻译：粘接垫结构及其制作方法
公开(公告)号：US07470994B2
公开(公告)日：2008-12-30
申请号：US11477940
申请日：2006-06-30
申请人： Tai-Chun Huang , Chih-Hsiang Yao , Chin-Chiu Hsia
发明人： Tai-Chun Huang , Chih-Hsiang Yao , Chin-Chiu Hsia
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/48463 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2224/05552 , H01L2224/45099
摘要： A semiconductor device includes a substrate with a dielectric layer thereon, a stack of interconnection structures in the dielectric layer, each interconnection structure including a conductive layer and a layer of plugs connecting the conductive layer, at least a layer of plugs including a crack stopper, and a bonding pad structure with a predetermined bump area thereon, overlying the stack of interconnection structures, wherein the crack stopper is formed along an edge of a projection area corresponding to the predetermined bump area.
摘要翻译：半导体器件包括其上具有介电层的衬底，电介质层中的互连结构的堆叠，每个互连结构包括导电层和连接导电层的插塞层，至少一个包括裂纹塞的塞子，以及在其上覆盖有互连结构的叠层的具有预定凸起区域的焊盘结构，其中所述裂纹阻挡件沿着与所述预定凹凸区域对应的投影区域的边缘形成。

32. 发明授权

US07074629B2 Test patterns for measurement of effective vacancy diffusion area 失效
标题翻译：用于测量有效空位扩散面积的测试模式
公开(公告)号：US07074629B2
公开(公告)日：2006-07-11
申请号：US11018604
申请日：2004-12-21
申请人： Chih-Hsiang Yao , Tai-Chun Huang
发明人： Chih-Hsiang Yao , Tai-Chun Huang
IPC分类号： G01R31/26
CPC分类号： H01L22/34
摘要： A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).
摘要翻译：测试图案（100,200,300,400,600,700）具有设置在基底（352）上的第一金属结构（102），设置在第一金属结构（102）上方的一个或多个中间层（358）和设置在所述一个或多个中间层（352）上方的第二金属结构（104）。第一通孔（106）穿过中间层（352）并将第一金属结构（102）连接到第二金属结构（104）。一个或多个第三金属结构（108）设置在一个或多个中间层（352）和第一金属结构（102）上方。一个或多个第二通孔（110）穿过中间层（352）并将第一金属结构（102）连接到第三金属结构（108）。第二通路（110）位于距离第一通孔（106）的中心的半径（R）的外侧。第三金属结构（110）通过介电材料（366）与第二金属结构（104）分离。

33. 发明申请

US20060055007A1 Seal ring structure for integrated circuit chips 有权
标题翻译：集成电路芯片的密封环结构
公开(公告)号：US20060055007A1
公开(公告)日：2006-03-16
申请号：US10940504
申请日：2004-09-13
申请人： Chih-Hsiang Yao , Tai-Chun Huang , Kuan-Shou Chi , Chih-Cherng Jeng , Ming-Shuoh Liang , Wen-Kai Wan , Chin-Chiu Hsia
发明人： Chih-Hsiang Yao , Tai-Chun Huang , Kuan-Shou Chi , Chih-Cherng Jeng , Ming-Shuoh Liang , Wen-Kai Wan , Chin-Chiu Hsia
IPC分类号： H01L23/552 , H01L23/12
CPC分类号： H01L21/78 , B28D5/0011 , H01L21/76224 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.
摘要翻译：公开了用于保护集成电路芯片的核心电路区域的密封环结构。密封圈结构包括具有桥接子层和插塞子层的金属化层。在集成电路芯片的外围边缘和核心电路区域之间的预定位置处，在桥接子层上形成上级桥。在与上层桥接器基本对准的插头子级上形成有较低级别的桥，其中下级桥具有与上级桥基本相同的宽度。

34. 发明申请

US20050158967A1 Semiconductor chip singulation method 有权
标题翻译：半导体芯片单片化方法
公开(公告)号：US20050158967A1
公开(公告)日：2005-07-21
申请号：US10761004
申请日：2004-01-20
申请人： Tai-Chun Huang , Kuan-Shou Chi , Chih-Hsiang Yao
发明人： Tai-Chun Huang , Kuan-Shou Chi , Chih-Hsiang Yao
IPC分类号： H01L21/301 , H01L21/46 , H01L21/78
CPC分类号： H01L21/78 , Y10S438/907
摘要： A method to singulate a circuit die from an integrated circuit wafer is achieved. The method comprises providing an integrated circuit wafer containing a circuit die. The integrated circuit wafer is cut through by performing a single, continuous cut around the perimeter of the circuit die to thereby singulate the circuit die.
摘要翻译：实现了从集成电路晶片中分离电路管芯的方法。该方法包括提供包含电路管芯的集成电路晶片。通过围绕电路管芯的周边执行单个连续的切割来切割集成电路晶片，从而对电路管芯进行分离。

35. 发明申请

US20050104224A1 Bond pad for flip chip package 有权
标题翻译：贴片垫用于倒装芯片封装
公开(公告)号：US20050104224A1
公开(公告)日：2005-05-19
申请号：US10716682
申请日：2003-11-19
申请人： Tai-Chun Huang , Chih-Hsiang Yao , Ching-Hua Hsieh
发明人： Tai-Chun Huang , Chih-Hsiang Yao , Ching-Hua Hsieh
IPC分类号： H01L23/485 , H01L29/40
CPC分类号： H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0401 , H01L2224/05093 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/351 , H01L2924/00 , H01L2224/48
摘要： A bond pad for a flip chip package. The bond pad is suitable for an integrated circuit chip. A plurality of slots are designed in the bond pad. Each of the slots extends along a direction which is perpendicular to a radial direction from the center of the bond pad. The bond pad is deposed at the corner of the integrated circuit chip.
摘要翻译：用于倒装芯片封装的焊盘。接合焊盘适用于集成电路芯片。在接合垫中设计多个槽。每个槽沿着从接合焊盘的中心垂直于径向的方向延伸。接合焊盘放在集成电路芯片的拐角处。

36. 发明授权

US08692351B2 Dummy shoulder structure for line stress reduction 有权
标题翻译：用于线应力降低的假肩结构
公开(公告)号：US08692351B2
公开(公告)日：2014-04-08
申请号：US12753272
申请日：2010-04-02
申请人： Cheng Cheng Kuo , Luke Lo , Minghsing Tsai , Ken-Yu Chang , Jye-Yen Cheng , Jeng-Shiun Ho , Hua-Tai Lin , Chih-Hsiang Yao
发明人： Cheng Cheng Kuo , Luke Lo , Minghsing Tsai , Ken-Yu Chang , Jye-Yen Cheng , Jeng-Shiun Ho , Hua-Tai Lin , Chih-Hsiang Yao
IPC分类号： H01L21/70
CPC分类号： H01L21/76838 , G06F17/5068 , G06F17/5072 , G06F17/5077 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.
摘要翻译：在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。所公开的结构包括半导体衬底和衬底上方的材料层。材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。

37. 发明申请

US20110092019A1 Method for Stacked Contact with Low Aspect Ratio 有权
标题翻译：堆叠接触方式与低纵横比
公开(公告)号：US20110092019A1
公开(公告)日：2011-04-21
申请号：US12973707
申请日：2010-12-20
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chih-Hsiang Yao , Wen-Kai Wan , Jye-Yen Cheng
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chih-Hsiang Yao , Wen-Kai Wan , Jye-Yen Cheng
IPC分类号： H01L21/60
CPC分类号： H01L23/485 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.
摘要翻译：集成电路结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成金属化层; 在所述半导体衬底和所述金属化层之间形成第一电介质层; 在所述半导体衬底和所述金属化层之间形成第二电介质层，其中所述第二电介质层在所述第一电介质层的上方; 以及形成具有基本上在所述第二介电层中的上部的接触塞和基本在所述第一介电层中的下部。接触插塞电连接到金属化层中的金属线。接触塞在上部和下部之间的界面处是不连续的。

38. 发明授权

US07777338B2 Seal ring structure for integrated circuit chips 有权
标题翻译：集成电路芯片的密封环结构
公开(公告)号：US07777338B2
公开(公告)日：2010-08-17
申请号：US10940504
申请日：2004-09-13
申请人： Chih-Hsiang Yao , Tai-Chun Huang , Kuan-Shou Chi , Chih-Cherng Jeng , Ming-Shuoh Liang , Wen-Kai Wan , Chin-Chiu Hsia
发明人： Chih-Hsiang Yao , Tai-Chun Huang , Kuan-Shou Chi , Chih-Cherng Jeng , Ming-Shuoh Liang , Wen-Kai Wan , Chin-Chiu Hsia
IPC分类号： H01L23/48
CPC分类号： H01L21/78 , B28D5/0011 , H01L21/76224 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.
摘要翻译：公开了用于保护集成电路芯片的核心电路区域的密封环结构。密封圈结构包括具有桥接子层和插塞子层的金属化层。在集成电路芯片的外围边缘和核心电路区域之间的预定位置处，在桥接子层上形成上层电桥。在与上层桥接器基本对准的插头子级上形成有较低级别的桥，其中下级桥具有与上级桥基本相同的宽度。

39. 发明授权

US07592710B2 Bond pad structure for wire bonding 有权
标题翻译：用于引线键合的焊盘结构
公开(公告)号：US07592710B2
公开(公告)日：2009-09-22
申请号：US11409297
申请日：2006-04-21
申请人： Chin-Chiu Hsia , Chih-Hsiang Yao , Tai-Chun Huang , Chih-Tang Peng
发明人： Chin-Chiu Hsia , Chih-Hsiang Yao , Tai-Chun Huang , Chih-Tang Peng
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/10 , H01L29/739 , H01L29/73 , H01L29/74
CPC分类号： H01L24/05 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05552 , H01L2224/05558 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48666 , H01L2224/48681 , H01L2224/48684 , H01L2224/48724 , H01L2224/48739 , H01L2224/48747 , H01L2224/48755 , H01L2224/48766 , H01L2224/48784 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2224/48781 , H01L2924/00012
摘要： A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate and is electrically coupled to the bond pad. The bond pad structure further includes a first passivation layer over the first dielectric layer wherein the first passivation layer has at least a portion under a middle portion of the bond pad. At least part of an active circuit is located under the bond pad.
摘要翻译：提供集成电路的接合焊盘结构。接合焊盘结构包括导电接合焊盘，接合焊盘下面的第一介电层和位于第一介电层中并位于接合焊盘下方的Mtop板。 Mtop板是固体导电板，并且电耦合到接合焊盘。所述接合焊盘结构还包括在所述第一电介质层上的第一钝化层，其中所述第一钝化层具有在所述接合焊盘的中间部分下方的至少一部分。有源电路的至少一部分位于接合焊盘下方。

40. 发明申请

US20070284747A1 INTEGRATED CIRCUIT HAVING IMPROVED INTERCONNECT STRUCTURE 有权
标题翻译：具有改进的互连结构的集成电路
公开(公告)号：US20070284747A1
公开(公告)日：2007-12-13
申请号：US11422769
申请日：2006-06-07
申请人： Chih-Hsiang Yao , Tai-Chun Huang , Mong-Song Liang
发明人： Chih-Hsiang Yao , Tai-Chun Huang , Mong-Song Liang
IPC分类号： H01L23/52
CPC分类号： H01L23/522 , H01L23/481 , H01L23/53228 , H01L23/5329 , H01L23/53295 , H01L2224/0401 , H01L2224/0557 , H01L2224/13023 , H01L2224/131 , H01L2924/0002 , H01L2924/13091 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： An improved integrated circuit structure and method of making the same is provided. The integrated circuit structure comprises a substrate, the substrate having a top surface and a bottom surface. The top surface has a circuit device formed thereon. The structure includes a plurality of metallization layers, a bonding structure formed over the bottom surface and a conductive interconnect structure formed through said substrate.
摘要翻译：提供了一种改进的集成电路结构及其制造方法。集成电路结构包括基板，该基板具有顶表面和底表面。顶表面上形成有电路装置。该结构包括多个金属化层，形成在底表面上的接合结构和通过所述衬底形成的导电互连结构。

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