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31. 发明授权

US08115263B2 Laminated silicon gate electrode 有权
标题翻译：层压硅栅电极
公开(公告)号：US08115263B2
公开(公告)日：2012-02-14
申请号：US11041178
申请日：2005-01-24
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L29/78
CPC分类号： H01L21/02532 , H01L21/02595 , H01L21/2022 , H01L21/28035 , H01L21/3003 , H01L29/4925 , H01L29/78
摘要： Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.
摘要翻译：在形成硅层的方法中，使用由较高结晶硅材料形成的至少一个子层和由下部结晶硅材料形成的至少一个子层。使用较高结晶硅材料的氢处理形成下部结晶硅材料。该方法对于形成具有增强尺寸控制和增强性能的多晶硅基栅电极特别有用。

32. 发明申请

US20080128835A1 Semiconductor Device Having a Random Grained Polysilicon Layer and a Method for its Manufacture 审中-公开
标题翻译：具有随机晶粒多晶硅层的半导体器件及其制造方法
公开(公告)号：US20080128835A1
公开(公告)日：2008-06-05
申请号：US11746366
申请日：2007-05-09
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L29/78
CPC分类号： H01L21/28044 , C23C16/24 , H01L21/0245 , H01L21/02532 , H01L21/02595 , H01L21/02609 , H01L21/0262 , H01L21/28052 , H01L29/4925
摘要： A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.
摘要翻译：提供了具有随机晶粒多晶硅层的半导体器件及其制造方法。在一个示例中，该器件在衬底上包括半导体衬底和绝缘体层。具有随机晶粒结构的第一多晶硅层位于绝缘体层的上方，半导体合金层位于第一多晶硅层的上方，第二多晶硅层位于半导体合金层的上方。

33. 发明申请

US20070240826A1 Gas supply device and apparatus for gas etching or cleaning substrates 审中-公开
标题翻译：用于气体蚀刻或清洁衬底的气体供应装置和装置
公开(公告)号：US20070240826A1
公开(公告)日：2007-10-18
申请号：US11405618
申请日：2006-04-18
申请人： Liang-Gi Yao , Chia-Lin Chen , Ming-Feng Wang , Ming-Feng Yoo , Kuen-Chyr Lee , Shih-Chang Chen
发明人： Liang-Gi Yao , Chia-Lin Chen , Ming-Feng Wang , Ming-Feng Yoo , Kuen-Chyr Lee , Shih-Chang Chen
IPC分类号： H01L21/306 , C23F1/00
CPC分类号： H01L21/67069
摘要： A gas supply device, including: a first source of an inert carrier gas, communicated with a first pipeline; a second source of anhydrous reactive gas, communicated with a second pipeline; a third source of enabling chemical gas of an enabling chemical compound, communicated with a third pipeline; a main pipeline, communicated with the first, second, and third pipelines; and a temperature controller, located on the second pipeline.
摘要翻译：一种气体供应装置，包括：与第一管道连通的惰性载气的第一源; 与第二管道连通的第二无水反应气源; 与第三管道连通的使能化学化合物化学气体的第三个来源; 一条主要管道，与第一条，第二条和第三条管道通信; 和位于第二管道上的温度控制器。

34. 发明授权

US06861339B2 Method for fabricating laminated silicon gate electrode 有权
标题翻译：叠层硅栅电极的制造方法
公开(公告)号：US06861339B2
公开(公告)日：2005-03-01
申请号：US10274570
申请日：2002-10-21
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/20 , H01L21/28 , H01L21/30 , H01L29/49 , H01L29/78 , H01L21/26
CPC分类号： H01L21/02532 , H01L21/02595 , H01L21/2022 , H01L21/28035 , H01L21/3003 , H01L29/4925 , H01L29/78
摘要： Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.
摘要翻译：在形成硅层的方法中，使用由较高结晶硅材料形成的至少一个子层和由下部结晶硅材料形成的至少一个子层。使用较高结晶硅材料的氢处理形成下部结晶硅材料。该方法对于形成具有增强尺寸控制和增强性能的多晶硅基栅电极特别有用。

35. 发明授权

US06780741B2 Method of forming a novel gate electrode structure comprised of a silicon-germanium layer located between random grained polysilicon layers 失效
标题翻译：形成由位于无规晶粒多晶硅层之间的硅 - 锗层构成的新型栅电极结构的方法
公开(公告)号：US06780741B2
公开(公告)日：2004-08-24
申请号：US10338155
申请日：2003-01-08
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L213205
CPC分类号： H01L21/28044 , H01L29/4925
摘要： A method of fabricating a gate structure for a MOSFET device, allowing a reduced polysilicon depletion effect as well as increased carrier mobility to be realized, has been developed. The method features a polysilicon-germanium component of the gate structure, sandwiched between an underlying polysilicon seed layer and an overlying polysilicon cap layer. The inclusion of germanium in the deposited polysilicon-germanium component results in enhanced dopant activation and thus a reduced polysilicon depletion effect. The polysilicon seed and cap layers are subjected to low temperature, anneal procedures, performed in situ in a hydrogen ambient, after deposition of the polysilicon layers. The in situ anneal procedures alters the columnar grains of the polysilicon layers to small, random grains resulting in smooth polysilicon surfaces, with the smooth surface of the polysilicon seed layer interfacing the underlying gate insulator layer resulting in enhanced carrier mobility when compared to counterpart polysilicon seed layer comprised with rough surfaces.
摘要翻译：已经开发了制造用于MOSFET器件的栅极结构的方法，其允许减少的多晶硅耗尽效应以及增加的载流子迁移率被实现。该方法具有栅极结构的多晶硅 - 锗组分，夹在下面的多晶硅种子层和上覆多晶硅覆盖层之间。在沉积的多晶硅 - 锗组分中包含锗导致增强的掺杂剂活化，从而减少了多晶硅的耗尽效应。多晶硅种子和盖层经过低温退火处理，在沉积多晶硅层之后在氢环境中原位进行。原位退火程序将多晶硅层的柱状晶体改变成小的随机晶粒，产生平滑的多晶硅表面，与对应的多晶硅晶粒相比，多晶硅籽晶层的平滑表面与下面的栅极绝缘体层相接触，导致增强的载流子迁移率层包含粗糙表面。

36. 发明授权

US07229919B2 Semiconductor device having a random grained polysilicon layer and a method for its manufacture 有权
标题翻译：具有随机晶粒多晶硅层的半导体器件及其制造方法
公开(公告)号：US07229919B2
公开(公告)日：2007-06-12
申请号：US10870878
申请日：2004-06-17
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/44
CPC分类号： H01L21/28044 , C23C16/24 , H01L21/0245 , H01L21/02532 , H01L21/02595 , H01L21/02609 , H01L21/0262 , H01L21/28052 , H01L29/4925
摘要： A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.
摘要翻译：提供了具有随机晶粒多晶硅层的半导体器件及其制造方法。在一个示例中，该器件在衬底上包括半导体衬底和绝缘体层。具有随机晶粒结构的第一多晶硅层位于绝缘体层的上方，半导体合金层位于第一多晶硅层的上方，第二多晶硅层位于半导体合金层的上方。

37. 发明授权

US07071066B2 Method and structure for forming high-k gates 失效
标题翻译：用于形成高k门的方法和结构
公开(公告)号：US07071066B2
公开(公告)日：2006-07-04
申请号：US10662845
申请日：2003-09-15
申请人： Ming-Fang Wang , Chia-Lin Chen , Chih-Wei Yang , Chi-Chun Chen , Tuo-Hung Hou , Yeou-Ming Lin , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Fang Wang , Chia-Lin Chen , Chih-Wei Yang , Chi-Chun Chen , Tuo-Hung Hou , Yeou-Ming Lin , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L29/513
摘要： A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.
摘要翻译：一种用于形成在栅极结构形成工艺中具有改进的电性能的改进的栅极堆叠结构的方法用于形成高介电常数栅极结构的方法，包括提供包括暴露表面部分的硅衬底; 在暴露的表面部分上形成具有小于约10埃的厚度的界面层; 在介电常数大于约10的界面层上形成高介电常数金属氧化物层; 在高介电常数金属氧化物层上形成阻挡层; 在阻挡层上形成电极层; 并且根据蚀刻图案通过电极层，阻挡层，高介电常数材料层和界面层的厚度进行蚀刻，以形成高介电常数栅极结构。

38. 发明授权

US07012009B2 Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process 失效
标题翻译：使用新型双温工艺改善硅/氧化物/多晶硅表面的硅 - 锗膜的电连续性的方法
公开(公告)号：US07012009B2
公开(公告)日：2006-03-14
申请号：US10785524
申请日：2004-02-24
申请人： Kuen-Chyr Lee , Liang-Gi Yao , Tien-Chih Chang , Chia-Lin Chen , Shih-Chang Chen , Mong-Song Liang
发明人： Kuen-Chyr Lee , Liang-Gi Yao , Tien-Chih Chang , Chia-Lin Chen , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/0245 , H01L21/02532
摘要： A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with shorter reaction times, and then growing an epitaxial Si—Ge layer with a Si cap layer at a lower temperature to form the intrinsic base with low boron out-diffusion. This results in an HBT having the desired narrow base profile while minimizing the discontinuities (voids) in the Si—Ge layer over the insulator to provide good electrical contacts and uniformity to the intrinsic base.
摘要翻译：在异质结双极晶体管的基极的基板上制造改进的硅 - 锗层的方法是使用双温工艺实现的。该方法包括在更高的温度下生长种子层以在较短的反应时间下降低晶粒尺寸，然后在较低温度下生长具有Si覆盖层的外延Si-Ge层以形成具有低硼外扩散的本征碱。这导致HBT具有期望的窄基底轮廓，同时最小化绝缘体上的Si-Ge层中的不连续性（空隙），以提供良好的电接触和对本征基底的均匀性。

39. 发明申请

US20050121671A1 Method for fabricating laminated silicon gate electrode 有权
公开(公告)号：US20050121671A1
公开(公告)日：2005-06-09
申请号：US11041178
申请日：2005-01-24
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/20 , H01L21/28 , H01L21/30 , H01L29/49 , H01L29/78 , H01L29/04 , H01L29/10 , H01L31/036 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02532 , H01L21/02595 , H01L21/2022 , H01L21/28035 , H01L21/3003 , H01L29/4925 , H01L29/78
摘要： Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.

40. 发明授权

US10683978B2 Lamp power assembling structure and method 有权
公开(公告)号：US10683978B2
公开(公告)日：2020-06-16
申请号：US16001920
申请日：2018-06-06
申请人： Chia-Lin Chen
发明人： Chia-Lin Chen
IPC分类号： F21S8/04 , F21K9/20 , F21V19/00 , F21S8/00 , F21V3/02 , F21Y105/18 , F21Y115/10 , F21V21/002 , H01R33/94 , H02G3/20 , H01R33/46 , F16M13/02
摘要： A lamp power assembling structure and method, the lamp power assembling structure is installed indoors and is connected an indoor power source, and includes a lamp power seat and a lamp fixing seat. The lamp power seat has a first power connector for connecting to the indoor power source and two sliding trenches. Each sliding trench has an arced channel and an enlarged hole formed at an end of the arced channel. The lamp fixing seat has a second power connector corresponding to the first power connector and two fasteners separately corresponding to the two enlarged holes. The two fasteners are separately inserted into the two enlarged holes, and the lamp fixing seat is rotated about the first and second power connectors so as to make the two fasteners separately to be engaged with the arced channels to fix the lamp fixing seat to the lamp power seat.

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