专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20060103439A1 Synchronization circuit and method with transparent latches 有权
公开(公告)号：US20060103439A1
公开(公告)日：2006-05-18
申请号：US11305433
申请日：2005-12-14
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： H03L7/06
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

32. 发明授权

US08296598B2 Double data rate output circuit and method 有权
标题翻译：双数据速率输出电路及方法
公开(公告)号：US08296598B2
公开(公告)日：2012-10-23
申请号：US13113550
申请日：2011-05-23
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： G06F1/12 , H03L7/00
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
摘要翻译：提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。第一透明锁存器接收与输入时钟同步的数据。第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

33. 发明申请

US20110228626A1 SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES 有权
标题翻译：同步电路的同步电路和方法
公开(公告)号：US20110228626A1
公开(公告)日：2011-09-22
申请号：US13113550
申请日：2011-05-23
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： G11C8/00 , H03L7/00
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
摘要翻译：提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。第一透明锁存器接收与输入时钟同步的数据。第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

34. 发明授权

US07334093B2 Block programmable priority encoder in a CAM 有权
标题翻译：在CAM中嵌入可编程优先编码器
公开(公告)号：US07334093B2
公开(公告)日：2008-02-19
申请号：US11673703
申请日：2007-02-12
申请人： Alan Roth , Sean Lord , Robert Mckenzie , Dieter Haerle , Steven Smith
发明人： Alan Roth , Sean Lord , Robert Mckenzie , Dieter Haerle , Steven Smith
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G11C15/00
摘要： A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.
摘要翻译：一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块具有最高优先级的数据输入。

35. 发明授权

US07062601B2 Method and apparatus for interconnecting content addressable memory devices 有权
标题翻译：用于互连内容可寻址存储器件的方法和装置
公开(公告)号：US07062601B2
公开(公告)日：2006-06-13
申请号：US10430378
申请日：2003-05-07
申请人： Oswald Becca , Alan Roth , Robert McKenzie
发明人： Oswald Becca , Alan Roth , Robert McKenzie
IPC分类号： G06F12/00
CPC分类号： G06F17/30982 , G06F13/18 , G06F13/4247 , G11C15/00
摘要： A cam system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMS in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for co-ordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimising the number of CAMs being connected to a common forwarding bus.
摘要翻译：一种凸轮系统，包括以串联级联装置连接的多个CAM装置，级联中的CAMS通过相应的转发总线连接到相邻的CAM，其中级联中的至多第一CAM连接到来自主机控制器和至多最后的CAM设备被耦合以将结果转发回主机控制器; 以及发送信号发生装置，用于向最后一个CAM提供SEND信号; 用于协调将搜索结果从最后一个CAM传送到主机控制器的SEND信号，串行级联布置使得连接到公共转发总线的CAM的数量最小化。

36. 发明授权

US07042746B2 Method and apparatus for performing variable word width searches in a content addressable memory 有权
公开(公告)号：US07042746B2
公开(公告)日：2006-05-09
申请号：US10902687
申请日：2004-07-30
申请人： Alan Roth
发明人： Alan Roth
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

37. 发明授权

US07010741B2 Method and circuit for error correction in CAM cells 有权
标题翻译： CAM单元纠错方法与电路
公开(公告)号：US07010741B2
公开(公告)日：2006-03-07
申请号：US10306732
申请日：2002-11-29
申请人： Richard Foss , Alan Roth
发明人： Richard Foss , Alan Roth
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C15/00
摘要： A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit; if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.
摘要翻译：提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读取并生成第一多个比特的奇偶校验，并将所生成的奇偶校验与存储的行奇偶校验位进行比较; 如果生成和存储的奇偶校验位不匹配，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

38. 发明授权

US07010713B2 Synchronization circuit and method with transparent latches 有权
公开(公告)号：US07010713B2
公开(公告)日：2006-03-07
申请号：US10352372
申请日：2003-01-27
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： G06F1/12 , G06F1/06
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

39. 发明授权

US09039278B2 Ratio meter of a thermal sensor 有权
标题翻译：热传感器的比率计
公开(公告)号：US09039278B2
公开(公告)日：2015-05-26
申请号：US13754151
申请日：2013-01-30
申请人： Mei-Chen Chuang , Jui-Cheng Huang , Alan Roth
发明人： Mei-Chen Chuang , Jui-Cheng Huang , Alan Roth
IPC分类号： G01K7/00 , G01L19/04 , G01R27/02 , G01K1/00
CPC分类号： G01K1/00 , G01K1/02 , G01K7/01 , G01K7/34 , G01K2219/00
摘要： A ratio meter includes a converter circuit, a first counter, a delay circuit, and a second counter. The converter circuit is configured to receive a temperature-independent signal, to convert the received temperature-independent signal into a first frequency signal during a first phase, to receive a temperature-dependent signal, and to convert the temperature-dependent signal into a second frequency signal during a second phase. The first counter is configured to receive the first frequency signal and to generate a control signal by counting a predetermined number of pulses of the first frequency signal count. The delay circuit is configured to delay the control signal for a predetermined time delay. The second counter is configured to receive the second frequency signal and to generate a count value by counting the second frequency signal.
摘要翻译：比率计包括转换器电路，第一计数器，延迟电路和第二计数器。转换器电路被配置为接收温度独立信号，以在第一阶段期间将接收到的与温度无关的信号转换为第一频率信号，以接收依赖于温度的信号，并将温度相关信号转换为第二频率信号频率信号在第二阶段。第一计数器被配置为接收第一频率信号并且通过对预定数量的第一频率信号计数的脉冲进行计数来产生控制信号。延迟电路被配置为延迟控制信号达预定的时间延迟。第二计数器被配置为接收第二频率信号并且通过对第二频率信号进行计数来产生计数值。

40. 发明授权

US08519684B2 Integrated circuits for converting a high voltage level to a low voltage level 有权
标题翻译：用于将高电压电平转换为低电压电平的集成电路
公开(公告)号：US08519684B2
公开(公告)日：2013-08-27
申请号：US12877535
申请日：2010-09-08
申请人： Mei-Chen Chuang , Alan Roth
发明人： Mei-Chen Chuang , Alan Roth
IPC分类号： G05F1/40
CPC分类号： H02M3/158 , G05F1/462 , H02M3/157 , H02M3/1588 , H05B33/0815 , Y02B70/1466
摘要： An integrated circuit includes a high side driver and a low side driver. The low side driver is electrically coupled with the high side driver. A circuit is electrically coupled with the high side driver and a first node between the high side driver and the low side driver. The circuit is configured to substantially turn off the high side driver if the high side driver leaves a cutoff region of the high side driver during a tri-state mode.
摘要翻译：集成电路包括高侧驱动器和低侧驱动器。低侧驱动器与高侧驱动器电耦合。电路与高侧驱动器和高侧驱动器和低侧驱动器之间的第一节点电耦合。如果高侧驱动器在三态模式期间离开高侧驱动器的截止区域，则该电路被配置为基本上关闭高侧驱动器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式