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31. 发明申请

US20060144698A1 ELECTROPLATING APPARATUS INCLUDING A REAL-TIME FEEDBACK SYSTEM 有权
标题翻译：包括实时反馈系统的电镀设备
公开(公告)号：US20060144698A1
公开(公告)日：2006-07-06
申请号：US10905361
申请日：2004-12-30
申请人： Chia-Lin Hsu , Kun-Hsien Lin , Wen-Chieh Su
发明人： Chia-Lin Hsu , Kun-Hsien Lin , Wen-Chieh Su
IPC分类号： B23H3/02 , C25B15/00
CPC分类号： C25D17/001 , C25D17/12 , C25D21/12
摘要： An electro-chemical plating system includes an upper rotor assembly for receiving and holding a wafer; an electroplating reactor vessel for containing plating solution in which the wafer is immersed; an anode array including a plurality of concentric anode segments provided inside the electroplating reactor vessel; a power supply system including power supply subunits for controlling electrical potentials of the anode segments, respectively; and a plurality of sensor devices mounted inside the upper rotor assembly, wherein the sensor devices are substantially arranged in corresponding to the anode segments, and during operation, the plurality of sensor devices are utilized for in-situ feeding back a deposition profile to a control unit in real time.
摘要翻译：电化学电镀系统包括用于接收和保持晶片的上转子组件; 电镀反应器容器，用于容纳浸有晶片的镀液; 阳极阵列，包括设置在所述电镀反应器容器内部的多个同心阳极段; 电源系统，包括分别用于控制阳极段的电位的电源子单元; 以及安装在上转子组件内部的多个传感器装置，其中传感器装置基本上布置成对应于阳极段，并且在操作期间，多个传感器装置用于将沉积轮廓原位反馈到控制器单位实时。

32. 发明授权

US06706140B2 Control system for in-situ feeding back a polish profile 失效
标题翻译：用于原位反馈抛光轮廓的控制系统
公开(公告)号：US06706140B2
公开(公告)日：2004-03-16
申请号：US09682486
申请日：2001-09-07
申请人： Chia-Lin Hsu , Shao-Chung Hu , Teng-Chun Tsai
发明人： Chia-Lin Hsu , Shao-Chung Hu , Teng-Chun Tsai
IPC分类号： B24B4900
CPC分类号： B24B37/04 , B24B49/10 , B24B57/02 , H01L21/30625
摘要： A chemical mechanical polishing (CMP) machine has a polish platen, having at least a first ring-shaped region and a second ring-shaped region. A control system for in-situ feeding back a polish profile of the CMP machine has at least a first sensor and a second sensor, respectively installed in the first and the second ring-shaped regions, and a control unit electrically connected to the first sensor and the second sensor for comparing the polish rates of portions of the wafer over the first and the second ring-shaped regions, respectively, according to signals of the first and the second sensors, and adjusting amounts of a slurry supplied by first and second slurry pump valves, corresponding to the first and second ring-shaped regions, according to a predetermined process, or adjusting forces loaded to the first and second regions of the wafer according to the predetermined process.
摘要翻译：化学机械抛光（CMP）机器具有抛光台板，具有至少第一环形区域和第二环形区域。用于原位反馈CMP机的抛光轮廓的控制系统具有分别安装在第一和第二环形区域中的至少第一传感器和第二传感器，以及电连接到第一传感器的控制单元以及第二传感器，用于根据第一和第二传感器的信号分别比较第一和第二环形区域上的部分晶片的抛光速率，以及调节由第一和第二浆料供应的浆料的量根据预定过程对应于第一和第二环形区域的泵阀，或根据预定过程加载到晶片的第一和第二区域的调节力。

33. 发明授权

US09318567B2 Fabrication method for semiconductor devices 有权
标题翻译：半导体器件制造方法
公开(公告)号：US09318567B2
公开(公告)日：2016-04-19
申请号：US13603425
申请日：2012-09-05
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chia-Lin Hsu
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chia-Lin Hsu
IPC分类号： H01L21/31 , H01L21/84 , H01L21/311 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.
摘要翻译：制造半导体器件的方法包括以下步骤。首先，提供至少包括翅片结构和至少设置在其上的栅极半导体层的半导体衬底。栅极半导体层覆盖翅片结构的一部分。然后沉积牺牲层以完全覆盖翅片结构。随后，翅片结构的顶表面通过蚀刻工艺从牺牲层露出。然后沉积材料层，其共形地覆盖栅极半导体层，鳍结构和牺牲层。最后，蚀刻材料层直到翅片结构的顶表面露出，并且在栅极半导体层的侧表面上同时形成第一间隔物。

34. 发明授权

US08796695B2 Multi-gate field-effect transistor and process thereof 有权
标题翻译：多栅极场效应晶体管及其工艺
公开(公告)号：US08796695B2
公开(公告)日：2014-08-05
申请号：US13530127
申请日：2012-06-22
申请人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号： H01L29/772
CPC分类号： H01L29/66795 , H01L29/1054 , H01L29/66484 , H01L29/785
摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
摘要翻译：多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。鳍状结构位于基板上。栅极结构设置在鳍状结构和衬底的一部分上。外延结构位于栅极结构旁边的鳍状结构上。梯度盖层位于每个外延结构上。梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

35. 发明授权

US08647986B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08647986B2
公开(公告)日：2014-02-11
申请号：US13220692
申请日：2011-08-30
申请人： Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
发明人： Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
IPC分类号： H01L21/306 , H01L21/321 , H01L21/3105 , H01L21/768
CPC分类号： H01L21/3212 , H01L21/3105 , H01L21/31051 , H01L21/31053 , H01L21/7684 , H01L21/823835 , H01L29/665
摘要： A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.
摘要翻译：半导体工艺包括以下步骤。第一栅极结构和第二栅极结构形成在基板上，其中第一栅极结构的顶部包括盖层，使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。在基板上形成介电层。执行第一化学机械抛光工艺以暴露盖层的顶表面。执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面，或执行蚀刻工艺以去除位于第二栅极结构上的介电层。然后执行第二化学机械抛光工艺以除去盖层。

36. 发明申请

US20130288448A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130288448A1
公开(公告)日：2013-10-31
申请号：US13459262
申请日：2012-04-30
申请人： Chin-I Liao , Chia-Lin Hsu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee , Min-Chung Cheng
发明人： Chin-I Liao , Chia-Lin Hsu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee , Min-Chung Cheng
IPC分类号： H01L21/762
CPC分类号： H01L21/0237 , H01L21/02532 , H01L21/02639 , H01L21/76224 , H01L29/66795
摘要： A semiconductor process includes the following steps. A semiconductor substrate is provided. The semiconductor substrate has a patterned isolation layer and the patterned isolation layer has an opening exposing a silicon area of the semiconductor substrate. A silicon rich layer is formed on the sidewalls of the opening. An epitaxial process is performed to form an epitaxial structure on the silicon area in the opening.
摘要翻译：半导体工艺包括以下步骤。提供半导体衬底。半导体衬底具有图案化隔离层，并且图案化隔离层具有暴露半导体衬底的硅区域的开口。在开口的侧壁上形成富硅层。执行外延工艺以在开口中的硅区域上形成外延结构。

37. 发明申请

US20130270612A1 Non-Planar FET and Manufacturing Method Thereof 有权
标题翻译：非平面FET及其制造方法
公开(公告)号：US20130270612A1
公开(公告)日：2013-10-17
申请号：US13447286
申请日：2012-04-16
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Chia-Lin Hsu
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Chia-Lin Hsu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7853 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/66795
摘要： The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
摘要翻译：本发明提供一种非平面FET，其包括衬底，鳍结构，栅极和栅极电介质层。翅片结构设置在基板上。翅片结构包括与基底相邻的第一部分，其中第一部分朝向基底的一侧收缩。门设置在翅片结构上。栅介质层设置在鳍结构和栅极之间。本发明还提供一种制造非平面FET的方法。

38. 发明申请

US20120244669A1 Method of Manufacturing Semiconductor Device Having Metal Gates 有权
标题翻译：制造具有金属门的半导体器件的方法
公开(公告)号：US20120244669A1
公开(公告)日：2012-09-27
申请号：US13053223
申请日：2011-03-22
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
摘要翻译：本发明提供一种制造具有金属栅极的半导体器件的方法。首先，提供基板。具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。去除第一牺牲栅极以形成第一沟槽。然后，在第一沟槽中形成第一金属层。去除第二牺牲栅极以形成第二沟槽。接下来，在第一沟槽和第二沟槽中形成第二金属层。最后，在第二金属层上形成第三金属层，其中第三金属层被填充到第一沟槽和第二沟槽中。

39. 发明申请

US20110189855A1 METHOD FOR CLEANING SURFACE CONTAINING Cu 审中-公开
标题翻译：清洗含Cu表面的方法
公开(公告)号：US20110189855A1
公开(公告)日：2011-08-04
申请号：US12699071
申请日：2010-02-03
申请人： Jen-Chieh Lin , Kai-Chun Yang , Chih-Yueh Li , Geng-Yu Fan , Jeng-Yu Fang , Teng-Chun Tsai , Chia-Lin Hsu
发明人： Jen-Chieh Lin , Kai-Chun Yang , Chih-Yueh Li , Geng-Yu Fan , Jeng-Yu Fang , Teng-Chun Tsai , Chia-Lin Hsu
IPC分类号： H01L21/306
CPC分类号： H01L21/306
摘要： A method for cleaning a surface is disclosed. First, a substrate including Cu and a barrier layer is provided. Second, a first chemical mechanical polishing procedure is performed on the substrate. Then, a second chemical mechanical polishing procedure is performed on the barrier layer. The second chemical mechanical polishing procedure includes performing a main chemical mechanical polishing procedure to partially remove the barrier layer and performing a chemical buffing procedure on the substrate using a chemical solution which has a pH value of about 6 to about 8 to remove residues on the substrate after the main chemical mechanical polishing procedure. Later, a water rinsing procedure is performed on the substrate. Afterwards, a post clean procedure is performed on the substrate after the second chemical mechanical polishing procedure.
摘要翻译：公开了一种清洁表面的方法。首先，提供包含Cu和阻挡层的基板。其次，在基板上进行第一化学机械抛光工序。然后，在阻挡层上进行第二化学机械抛光工序。第二化学机械抛光方法包括执行主要的化学机械抛光方法以部分去除阻挡层并使用pH值为约6至约8的化学溶液在基底上进行化学抛光过程以去除基底上的残留物经过主要的化学机械抛光程序。之后，在基板上进行水洗工序。之后，在第二化学机械抛光程序之后，在基板上执行后清洁程序。

40. 发明授权

US07718536B2 Planarization process for pre-damascene structure including metal hard mask 有权
标题翻译：包括金属硬掩模在内的前镶嵌结构的平面化处理
公开(公告)号：US07718536B2
公开(公告)日：2010-05-18
申请号：US11160262
申请日：2005-06-16
申请人： Chia-Lin Hsu
发明人： Chia-Lin Hsu
IPC分类号： H01L21/461
CPC分类号： H01L21/3212
摘要： A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.
摘要翻译：描述了一种预镶嵌结构的平面化方法，其中预镶嵌结构包括设置在其中具有镶嵌开口的第一材料层上的金属硬掩模和填充镶嵌开口并覆盖金属的第二材料层硬面膜使用第一浆料进行第一CMP步骤以除去镶嵌开口外部的第二材料层。使用第二浆料进行第二CMP步骤以除去金属硬掩模。

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