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31. 发明授权

US06414315B1 Radiation imaging with continuous polymer layer for scintillator 失效
标题翻译：用于闪烁体的连续聚合物层的辐射成像
公开(公告)号：US06414315B1
公开(公告)日：2002-07-02
申请号：US09411299
申请日：1999-10-04
申请人： Ching-Yeu Wei , Robert Forrest Kwasnick , David Francis Fobare
发明人： Ching-Yeu Wei , Robert Forrest Kwasnick , David Francis Fobare
IPC分类号： G01T1202
CPC分类号： G01T1/2018
摘要： A radiation imager includes a light sensitive imaging array, a barrier layer formed over the light sensitive imaging array, a continuous polymer layer formed over the barrier layer, and a scintillator formed directly on the continuous polymer layer. The continuous polymer layer improves the adherence of the scintillator by reducing delamination especially under adverse environmental conditions.
摘要翻译：辐射成像仪包括光敏成像阵列，在光敏成像阵列上形成的阻挡层，形成在阻挡层上的连续聚合物层，以及直接形成在连续聚合物层上的闪烁体。连续聚合物层通过减少分层改善闪烁体的粘附，特别是在不利的环境条件下。

32. 发明授权

US5518956A Method of isolating vertical shorts in an electronic array using laser ablation 失效
标题翻译：使用激光烧蚀隔离电子阵列中的垂直短路的方法
公开(公告)号：US5518956A
公开(公告)日：1996-05-21
申请号：US115082
申请日：1993-09-02
申请人： Yung S. Liu , Renato Guida , Ching-Yeu Wei
发明人： Yung S. Liu , Renato Guida , Ching-Yeu Wei
IPC分类号： B23K26/00 , G02F1/1362 , H01L21/48 , H01L21/768 , H01L27/14 , H05K3/22 , H01L21/26
CPC分类号： H01L21/76894 , H01L21/485 , H05K3/225 , G02F1/1362 , Y10S438/94
摘要： A process for repairing an electronic army wafer assembly having a short circuit between two non-insulative layers separated by a dielectric layer includes the step of selectively ablating one of the non-insulative layers so as to electrically isolate the situs of the short circuit while maintaining the electrical integrity of the underlying non-insulative layer intact. A laser beam is directed onto the non-insulative layer and scanned in a selected pattern to isolate the situs of the short circuit; the laser is further controlled such that a selected energy density is delivered to the surface to be ablated such that the underlying non-insulative layer is not damaged.
摘要翻译：修复由电介质层分离的两个非绝缘层之间具有短路的电子军团晶片组件的工艺包括选择性地烧蚀非绝缘层之一以使电路的位置电隔离的步骤，同时保持底层非绝缘层的电气完整性完好无损。激光束被引导到非绝缘层上并以选定的图案扫描以隔离短路的位置; 进一步控制激光，使得所选择的能量密度被输送到要消融的表面，使得下面的非绝缘层不被损坏。

33. 发明授权

US5516712A Method of fabricating radiation imager with single passivation dielectric for transistor and diode 失效
标题翻译：用于晶体管和二极管制造单个钝化电介质的辐射成像仪的方法
公开(公告)号：US5516712A
公开(公告)日：1996-05-14
申请号：US330955
申请日：1994-10-28
申请人： Ching-Yeu Wei , Robert F. Kwasnick , Brian W. Giambattista
发明人： Ching-Yeu Wei , Robert F. Kwasnick , Brian W. Giambattista
IPC分类号： H01L21/77 , H01L21/84 , H01L27/12 , H01L27/146 , H01L27/15 , H01L29/786 , H01L31/10
CPC分类号： H01L27/14643 , H01L27/1214
摘要： A radiation imager includes a photosensor array having a plurality of individually addressable pixels, each pixel having a photosensor island and an associated thin film transistor (TFT) disposed to selectively electrically couple the photosensor island to a predetermined address line. In each pixel a single common passivation layer is disposed over the TFT and the photosensor island such that the passivation layer is adjacent to both the outer surfaces of the TFT and portions of the photosensor island. In a method of fabricating a photosensor array as described above, after depositon of a source-drain metal layer, the layer is left unpatterned until after the photosensor island has been formed. In the formation of the photosensor island the source-drain metal layer serves as an etch stop to protect the TFT. Following formation of the photosensor island, the source-drain metal layer is patterned to form source and drain electrodes and fabrication of the TFT is completed. The single common passivation layer is then deposited over both the TFT and the photosensor island.
摘要翻译：辐射成像仪包括具有多个可独立寻址的像素的光电传感器阵列，每个像素具有光电传感器岛和相关联的薄膜晶体管（TFT），用于选择性地将光电传感器岛电耦合到预定的地址线。在每个像素中，单个公共钝化层设置在TFT和光电传感器岛上，使得钝化层与TFT的外表面和光电传感器岛的两个部分相邻。在如上所述的制造光电传感器阵列的方法中，在源极 - 漏极金属层沉积之后，该层被保持未图案化，直到形成光电传感器岛为止。在光电传感器岛的形成中，源极 - 漏极金属层用作蚀刻停止以保护TFT。在形成光电传感器岛之后，对源极 - 漏极金属层进行图案化以形成源极和漏极并完成TFT的制造。然后将单个公共钝化层沉积在TFT和光电传感器岛上。

34. 发明授权

US5475246A Repair line structure for thin film electronic devices 失效
标题翻译：维修薄膜电子设备的线路结构
公开(公告)号：US5475246A
公开(公告)日：1995-12-12
申请号：US169290
申请日：1993-12-20
申请人： Ching-Yeu Wei , Roger S. Salisbury , Robert F. Kwasnick
发明人： Ching-Yeu Wei , Roger S. Salisbury , Robert F. Kwasnick
IPC分类号： G02F1/1362 , H01L21/768 , H01L21/82 , H01L23/522 , H01L23/525 , H01L27/146 , H01L27/10 , H01L27/15
CPC分类号： H01L27/146 , H01L21/76892 , H01L23/525 , G02F2001/136263 , H01L2924/0002
摘要： Repair lines in an imager device include protective layers disposed over steps in the repair lines where the repair lines extend over underlying components in the imager array. The protective layers each include a layer of polyimide to provide protection for the step portions of the conductive repair line from etchants and the like to which the conductive line is exposed during fabrication processes for the imager array. The protective layers are disposed over the steps of a conductive line in a repair crossover region so as to provide a repair area free from the protective material of the protective layers disposed thereon in the repair crossover region where the conductive repair line is disposed in vertical alignment with an underlying address line.
摘要翻译：成像设备中的修复线包括设置在修复线上的步骤之上的保护层，其中修复线延伸到成像器阵列中的下面的部件上。保护层各自包括聚酰亚胺层，以便在成像器阵列的制造过程期间为导电线暴露的蚀刻剂等提供对导电修补线的台阶部分的保护。保护层设置在修复交叉区域中的导电线的台阶上，以便提供修复区域，该修复区域不设置在修复交叉区域中的保护层的保护材料，其中导电修复线设置成垂直对准与底层地址行。

35. 发明授权

US5463225A Solid state radiation imager with high integrity barrier layer and method of fabricating 失效
标题翻译：具有高完整性阻挡层的固态辐射成像仪
公开(公告)号：US5463225A
公开(公告)日：1995-10-31
申请号：US99370
申请日：1993-07-29
申请人： Robert F. Kwasnick , Ching-Yeu Wei , Jack D. Kingsley
发明人： Robert F. Kwasnick , Ching-Yeu Wei , Jack D. Kingsley
IPC分类号： G01J1/02 , G01T1/20 , H01L27/146 , H01L31/0216 , H01L31/0232 , H01L31/105 , H01L31/055
CPC分类号： H01L31/0216 , H01L31/02322 , H01L31/1055
摘要： A radiation imager includes a photosensor barrier layer disposed between an amorphous silicon photosensor array and the scintillator. The barrier layer includes two strata, the first stratum being silicon oxide disposed over the upper conductive layer of the photosensor array and the second stratum is silicon nitride that is disposed over the first stratum. The photosensor barrier layer has a shape that substantially conforms to the the shape of the underlying upper conductive layer and has a maximum thickness of about 3 microns. The silicon oxide and silicon nitride are deposited in a vapor deposition process at less than about 250.degree. C. using tetraethoxysilane (TEOS) as the silicon source gas.
摘要翻译：辐射成像仪包括设置在非晶硅光电传感器阵列和闪烁体之间的光电传感器阻挡层。阻挡层包括两层，第一层是设置在光传感器阵列的上导电层上的氧化硅，第二层是设置在第一层上的氮化硅。光电传感器阻挡层具有基本上符合下面的上导电层的形状并具有约3微米的最大厚度的形状。使用四乙氧基硅烷（TEOS）作为硅源气体，在小于约250℃的气相沉积工艺中沉积氧化硅和氮化硅。

36. 发明授权

US5241192A Fabrication method for a self-aligned thin film transistor having reduced end leakage and device formed thereby 失效
标题翻译：具有减小的端部泄漏的自对准薄膜晶体管的制造方法以及由此形成的器件
公开(公告)号：US5241192A
公开(公告)日：1993-08-31
申请号：US862125
申请日：1992-04-02
申请人： George E. Possin , Ching-Yeu Wei
发明人： George E. Possin , Ching-Yeu Wei
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/786
CPC分类号： H01L29/78696 , H01L27/1214 , H01L29/66765 , Y10S438/978
摘要： The TFT structure formed in accordance with this invention includes a TFT body that has channel plug end sidewalls separated by a distance equal to or less than the width of the source/drain address lines and such that no residual doped semiconductor material adheres to the sidewalls. Similarly, the intrinsic semiconductor material layer is shaped such that no residual doped semiconductor material adheres to the sidewalls of the intrinsic semiconductor material layer underlying the channel plug ends.
摘要翻译：根据本发明形成的TFT结构包括TFT体，其具有分隔等于或小于源极/漏极地址线的宽度的距离的通道插塞端侧壁，并且使得没有残留的掺杂半导体材料粘附到侧壁。类似地，本征半导体材料层被成形为使得没有残留掺杂的半导体材料粘附到通道插塞下面的本征半导体材料层的侧壁终止。

37. 发明授权

US5187369A High sensitivity, high resolution, solid state x-ray imaging device with barrier layer 失效
标题翻译：高灵敏度，高分辨率，具有障碍层的固态X射线成像装置
公开(公告)号：US5187369A
公开(公告)日：1993-02-16
申请号：US762708
申请日：1991-09-19
申请人： Jack D. Kingsley , Robert F. Kwasnick , Ching-Yeu Wei , Richard J. Saia
发明人： Jack D. Kingsley , Robert F. Kwasnick , Ching-Yeu Wei , Richard J. Saia
IPC分类号： H01L27/14 , G01T1/20 , H01L27/146 , H01L31/09
CPC分类号： H01L27/14663
摘要： A radiation imager includes a photodetector array having topographically patterned surface features, which include support islands disposed over the active portion of one or more photodetectors in the photodetector array. A structured scintillator array having individual columnar scintillator elements is disposed in fixed relation to the photodetector array so that the individual scintillator elements are disposed on scintillator support islands. A barrier layer is disposed between the support islands and the photodetector array to minimize chemical interactions between the material forming the support island and the underlying photodetector array during the fabrication process. After the support islands have been patterned, the scintillator elements are grown by selectively depositing scintillator material on the support islands.
摘要翻译：辐射成像仪包括具有地形图案化的表面特征的光电检测器阵列，其包括设置在光电检测器阵列中的一个或多个光电探测器的有效部分之上的支撑岛。具有单个柱状闪烁体元件的结构闪烁体阵列以固定的关系设置在光电检测器阵列上，使得各个闪烁体元件设置在闪烁体支撑岛上。阻挡层设置在支撑岛和光电检测器阵列之间，以最小化在制造过程中形成支撑岛的材料与下面的光电检测器阵列之间的化学相互作用。在支撑岛被图案化之后，通过在支撑岛上选择性地沉积闪烁体材料来生长闪烁体元件。

38. 发明授权

US5156986A Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration 失效
标题翻译：通过顶帽栅极电极配置对自对准TFTS中的源极/漏极 - 栅极重叠进行正向控制
公开(公告)号：US5156986A
公开(公告)日：1992-10-20
申请号：US667149
申请日：1991-03-11
申请人： Ching-Yeu Wei , George E. Possin , Robert F. Kwasnick
发明人： Ching-Yeu Wei , George E. Possin , Robert F. Kwasnick
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66765 , H01L21/28008 , H01L29/42384 , H01L29/4908
摘要： Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.
摘要翻译：通过包括具有不同蚀刻特性的两个不同导体的栅极导体层来提供薄膜晶体管中的栅极电极和源极和漏极之间的重叠长度的正向控制。作为栅极导体图案定义过程的一部分，蚀刻两个栅极导体以暴露下面的材料，并且根据栅电极和源之间的期望重叠，蚀刻回去上栅极导体层以暴露第一栅极导体层，以及漏电极。此后，使用平面化和非选择性蚀刻方法，用相对于第二栅极导体层自对准的源极和漏极制造器件的其余部分。

39. 发明授权

US4859620A Graded extended drain concept for reduced hot electron effect 失效
标题翻译：分级扩展漏极概念，减少热电子效应
公开(公告)号：US4859620A
公开(公告)日：1989-08-22
申请号：US196416
申请日：1988-05-20
申请人： Ching-Yeu Wei , Joseph M. Pimbley
发明人： Ching-Yeu Wei , Joseph M. Pimbley
IPC分类号： H01L21/225 , H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/2253 , H01L21/2652 , H01L29/78 , Y10S257/90 , Y10S438/965
摘要： Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a graded, buried spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur.
摘要翻译：对MOSFET器件的栅极氧化物的热电子注入对VLSI电路中的这种器件的小型化造成了限制。提供具有分级埋置间隔物的掩埋通道以防止热电子捕获效应，同时保持与微米或亚微米VLSI器件的工艺和结构相容性。沟道电流在远离热电子效应最可能发生的漏极区附近的界面的一定距离被重定向到掩埋沟道。

40. 发明授权

US4680603A Graded extended drain concept for reduced hot electron effect 失效
标题翻译：分级扩展漏极概念，减少热电子效应
公开(公告)号：US4680603A
公开(公告)日：1987-07-14
申请号：US722640
申请日：1985-04-12
申请人： Ching-Yeu Wei , Joseph M. Pimbley
发明人： Ching-Yeu Wei , Joseph M. Pimbley
IPC分类号： H01L21/225 , H01L21/265 , H01L21/336 , H01L29/423 , H01L29/78 , H01L29/08 , H01L29/36
CPC分类号： H01L29/6659 , H01L21/2253 , H01L21/2652 , H01L29/78
摘要： Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a graded, buried spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur.
摘要翻译：对MOSFET器件的栅极氧化物的热电子注入对VLSI电路中的这种器件的小型化造成了限制。提供具有分级埋置间隔物的掩埋通道以防止热电子捕获效应，同时保持与微米或亚微米VLSI器件的工艺和结构相容性。沟道电流在远离热电子效应最可能发生的漏极区附近的界面的一定距离被重定向到掩埋沟道。

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