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31. 发明授权

US4264693A Light and current sensitive film and print-display system therewith 失效
标题翻译：光和电流敏感的薄膜和印刷显示系统
公开(公告)号：US4264693A
公开(公告)日：1981-04-28
申请号：US974640
申请日：1978-12-29
申请人： Barbara A. Gardineer , Carlos J. Sambucetti , Hugo K. Seitz
发明人： Barbara A. Gardineer , Carlos J. Sambucetti , Hugo K. Seitz
IPC分类号： B41M5/20 , G03C1/725 , G03G5/00 , G03G17/00
CPC分类号： B41M5/20 , G03C1/725 , G03C1/7253 , G03C1/7256 , Y10S428/913 , Y10T428/256 , Y10T428/31996
摘要： Films are disclosed which are constituted essentially of iodides of heavy metals to which catalysts or sensitizing agents are added to make the films highly sensitive to light and current at room temperature, thus increasing the speed of writing and erasing cycles. The disclosure provides for producing and erasing images on such light and current sensitive films prepared on substrates such as ordinary paper or transparent non-reactive materials. Marking on the films is achieved by light e.g., laser beam and Xenon lamp, or electrical current. Exemplary erasing is done by application of heat. Several examples are disclosed of the formation of these films adherently on non-reactive surfaces.
摘要翻译：公开了基本上由重金属的碘化物构成的膜，其中加入催化剂或增感剂以使膜在室温下对光和电流高度敏感，从而增加写入和擦除循环的速度。本公开提供了在诸如普通纸或透明非反应性材料的基底上制备的这种光和电流敏感膜上产生和擦除图像。膜上的标记通过光例如激光束和氙灯或电流来实现。通过施加热来进行示例性擦除。公开了在非反应性表面上粘附形成这些膜的几个实例。

32. 发明授权

US06566612B2 Method for direct chip attach by solder bumps and an underfill layer 有权
公开(公告)号：US06566612B2
公开(公告)日：2003-05-20
申请号：US10055294
申请日：2002-01-22
申请人： Guy P. Brouillette , David H. Danovitch , Peter A. Gruber , Michael Liehr , Carlos J. Sambucetti
发明人： Guy P. Brouillette , David H. Danovitch , Peter A. Gruber , Michael Liehr , Carlos J. Sambucetti
IPC分类号： H01R909
CPC分类号： H01L21/563 , H01L2224/73203 , H01L2224/81191 , H01L2224/83192 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , H01L2924/00
摘要： A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads. In the bonded assembly, the in-situ polymeric mold layer and the underfill material layer forms a composite underfill to replace a conventional underfill material that must be injected between bonded chip and substrate by a capillary action in a time consuming process.

33. 发明授权

US06358832B1 Method of forming barrier layers for damascene interconnects 有权
标题翻译：形成大马士革互连的阻挡层的方法
公开(公告)号：US06358832B1
公开(公告)日：2002-03-19
申请号：US09641834
申请日：2000-08-18
申请人： Daniel C. Edelstein , Timothy J. Dalton , John G. Gaudiello , Mahadevaiyer Krishnan , Sandra G. Malhotra , Maurice McGlashan-Powell , Eugene J. O'Sullivan , Carlos J. Sambucetti
发明人： Daniel C. Edelstein , Timothy J. Dalton , John G. Gaudiello , Mahadevaiyer Krishnan , Sandra G. Malhotra , Maurice McGlashan-Powell , Eugene J. O'Sullivan , Carlos J. Sambucetti
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/288 , H01L21/3212 , H01L21/76829 , H01L21/76834 , H01L21/76835
摘要： A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.
摘要翻译：包含双蚀刻停止/扩散屏障的镶嵌互连。镶嵌互连的导电材料用导电金属扩散阻挡盖（通常使用无电沉积）和可选地与电介质蚀刻停止层封盖。还可以存在任选的化学机械抛光 - 停止层。本发明的不同方法允许不同层的CMP停止，反应离子蚀刻停止和金属扩散阻挡层要求被去耦合。优选的导电材料是铜。

34. 发明授权

US06341418B1 Method for direct chip attach by solder bumps and an underfill layer 有权
标题翻译：通过焊料凸块和底部填充层直接贴片的方法
公开(公告)号：US06341418B1
公开(公告)日：2002-01-29
申请号：US09301890
申请日：1999-04-29
申请人： Guy P. Brouillette , David H. Danovitch , Peter A. Gruber , Michael Liehr , Carlos J. Sambucetti
发明人： Guy P. Brouillette , David H. Danovitch , Peter A. Gruber , Michael Liehr , Carlos J. Sambucetti
IPC分类号： H05K334
CPC分类号： H01L21/563 , H01L2224/73203 , H01L2224/81191 , H01L2224/83192 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , H01L2924/00
摘要： A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads. In the bonded assembly, the in-situ polymeric mold layer and the underfill material layer forms a composite underfill to replace a conventional underfill material that must be injected between bonded chip and substrate by a capillary action in a time consuming process.
摘要翻译：公开了一种通过使用焊料凸块和底部填充层将半导体芯片直接贴合到电路板的方法。在该方法中，首先在半导体芯片的顶表面上丝网印刷一层原位聚合物模材料，暴露出多个接合焊盘。原位聚合物模具层形成有多个孔，然后在熔融焊料筛选过程中用焊料材料填充以形成焊料凸块。然后将薄的含有焊剂的底层填充材料层放置在电路板的顶部上，该多个导电焊盘以镜像形式布置在半导体芯片上的接合焊盘上。然后将半导体芯片和电路板与其中的底部填充层一起压在一起，并被加热到高于焊料材料的熔融温度的回流温度，直到在焊盘和导电焊盘之间建立电连通。在粘合组件中，原位聚合物模层和底部填充材料层形成复合底层填料，以代替在耗时的过程中必须通过毛细管作用在粘合的芯片和衬底之间注入的常规底部填充材料。

35. 发明授权

US5866044A Lead free conductive composites for electrical interconnections 失效
标题翻译：无铅导电复合材料用于电气互连
公开(公告)号：US5866044A
公开(公告)日：1999-02-02
申请号：US734492
申请日：1996-10-21
申请人： Ravi F. Saraf , Judith Marie Roldan , Michael Anthony Gaynes , Richard Benton Booth , Steven Paul Ostrander , Emanuel I. Cooper , Carlos J. Sambucetti
发明人： Ravi F. Saraf , Judith Marie Roldan , Michael Anthony Gaynes , Richard Benton Booth , Steven Paul Ostrander , Emanuel I. Cooper , Carlos J. Sambucetti
IPC分类号： H01B1/22 , H01L21/60 , H01L23/498 , H05K3/32 , H05K3/46 , H01B1/12
CPC分类号： H01L24/81 , H01B1/22 , H01L23/49883 , H05K3/321 , H01L2224/13009 , H01L2224/81801 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K2201/0129 , H05K2201/0133 , H05K2201/0162 , H05K2203/0783 , H05K3/4614 , H05K3/4632
摘要： An electrically conductive paste which includes a thermoplastic polymer, a conductive metal powder and an organic solvent system is disclosed. The invention further encompasses an electrically conductive composite which includes the aforementioned thermoplastic and metal, wherein the metal represents at least about 30% by volume, based on the total volume of the composite. The composite is formed from the paste under elevated temperature. The paste is employed in processes which involve electrically connecting electrical and electronic components under process conditions which convert the paste to the composite.
摘要翻译：公开了一种包括热塑性聚合物，导电金属粉末和有机溶剂系统的导电浆料。本发明还包括一种包含上述热塑性和金属的导电复合材料，其中基于复合材料的总体积，金属占体积的至少约30体积％。复合材料由高温下的糊料形成。该糊剂用于涉及将糊料转化为复合材料的工艺条件下的电气和电子部件电连接的工艺。

36. 发明授权

US5079070A Repair of open defects in thin film conductors 失效
标题翻译：修复薄膜导体中的开放缺陷
公开(公告)号：US5079070A
公开(公告)日：1992-01-07
申请号：US595902
申请日：1990-10-11
申请人： Pedro A. Chalco , Carlos J. Sambucetti
发明人： Pedro A. Chalco , Carlos J. Sambucetti
IPC分类号： B23K20/10 , B23K26/32 , G02F1/13 , H05K3/20 , H05K3/22 , H05K3/24 , H05K3/32 , H05K3/46
CPC分类号： H05K3/225 , B23K20/10 , G02F1/1309 , H05K2201/0317 , H05K2201/1028 , H05K2203/0278 , H05K2203/0285 , H05K2203/107 , H05K2203/173 , H05K3/20 , H05K3/244 , H05K3/328 , Y10S428/901 , Y10S428/913 , Y10T428/24917 , Y10T428/31678 , Y10T428/31721
摘要： Open defects in thin film conductor lines on a substrate are repaired by diffusion bonding a selected conductive repair line from a support sheet positioned over the open defect. The diffusion bonding is performed by the application of ultrasonic energy and laser energy.
摘要翻译：通过将所选择的导电修复线从位于开放缺陷上的支撑片扩散接合来修复衬底上的薄膜导体线中的开放缺陷。通过施加超声能量和激光能量来进行扩散接合。

37. 发明授权

US4478883A Conditioning of a substrate for electroless direct bond plating in holes and on surfaces of a substrate 失效
标题翻译：调理用于无孔直接结合电镀的基板在孔和基板的表面上
公开(公告)号：US4478883A
公开(公告)日：1984-10-23
申请号：US398140
申请日：1982-07-14
申请人： James R. Bupp , Voya Markovich , Tracy E. Napp , Carlos J. Sambucetti
发明人： James R. Bupp , Voya Markovich , Tracy E. Napp , Carlos J. Sambucetti
IPC分类号： H05K3/18 , C23C18/18 , C23C18/20 , C23C18/30 , H05K3/38 , C23C3/02
CPC分类号： H05K3/381 , C23C18/1858 , C23C18/1865 , C23C18/1893
摘要： A dielectric surface is conditioned for electroless plating of a conductive metal thereon by contacting the surface with a multifunctional ionic copolymer. The conditioning can be in the holes and/or on the surfaces of the substrate.
摘要翻译：通过使表面与多功能离子共聚物接触，对电介质表面进行调理，以使其上的导电金属化学镀。调理可以在基底的孔和/或表面上。

38. 发明授权

US4448804A Method for selective electroless plating of copper onto a non-conductive substrate surface 失效
标题翻译：铜在非导电基材表面上的选择性化学镀电镀方法
公开(公告)号：US4448804A
公开(公告)日：1984-05-15
申请号：US540600
申请日：1983-10-11
申请人： William J. Amelio , Gary K. Lemon , Voya Markovich , Theodore Panasik , Carlos J. Sambucetti , Donna J. Trevitt
发明人： William J. Amelio , Gary K. Lemon , Voya Markovich , Theodore Panasik , Carlos J. Sambucetti , Donna J. Trevitt
IPC分类号： C23C18/16 , C23C18/40 , C23C18/52 , H05K3/18 , H05K3/38 , B05D5/12 , B05D1/32 , B05D3/04 , C23F1/00
CPC分类号： H05K3/381 , C23C18/1605 , C23C18/1651 , C23C18/1893 , C23C18/2086 , C23C18/285 , C23C18/30 , C23C18/405 , H05K3/181 , H05K2203/1407
摘要： Multistep process for electroless plating of copper onto a non-conductive surface including the steps of: (1) laminating a rough copper sheet onto the non-conductive surface; (2) etching away all the copper; (3) conditioning the surface with multifunctional positively charged molecules derived from copolymers of polyacrylamide and functionally active tetraalkylammonium compounds in an diluted inorganic acid; (4) activating the conditioned surface preferably with stannous/palladium chloride particles; (5) treating the activated surface with deionized water and diluted HCl; (6) applying a photoresist layer to the surface and selectively exposing and developing the photoresist to produce a mask corresponding to the negative of the desired circuit pattern; and (7) plating copper using successively two baths differing in their oxygen and CN.sup.- concentration, where the foregoing steps are interspersed with washing steps.
摘要翻译：包括以下步骤：（1）将铜铜层压到非导电表面上; （2）蚀刻所有铜; （3）用稀释的无机酸中的聚丙烯酰胺和功能活性四烷基铵化合物的共聚物衍生的多官能带正电的分子调理表面; （4）优选用亚锡/氯化钯粒子活化调理表面; （5）用去离子水和稀HCl稀释活化表面; （6）将光致抗蚀剂层施加到表面并选择性地曝光和显影光致抗蚀剂以产生对应于所需电路图案的负片的掩模; 和（7）使用连续两个不同氧气和CN-浓度的浴电镀铜，其中上述步骤穿过洗涤步骤。

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