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31. 发明授权

US06418496B2 System and apparatus including lowest priority logic to select a processor to receive an interrupt message 失效
标题翻译：包括用于选择处理器以接收中断消息的最低优先级逻辑的系统和装置
公开(公告)号：US06418496B2
公开(公告)日：2002-07-09
申请号：US08988233
申请日：1997-12-10
申请人： Stephen S. Pawlowski , Daniel G. Lau
发明人： Stephen S. Pawlowski , Daniel G. Lau
IPC分类号： G06F1324
CPC分类号： G06F13/26
摘要： One embodiment of the invention includes an apparatus, such as a bridge, for use in connection a with computer system. The apparatus includes remote priority capture logic to hold task priority data indicative of a task priority of each processor in the computer system that is available for lowest priority interrupt destination arbitration (LPIDA). The apparatus also includes lowest priority logic to perform the LPIDA to select processor in the computer system is to receive an interrupt message based on contents of the remote priority capture logic. Another embodiment of the invention includes a multi-processor system having processors and a processor bus coupled to the processors. The system includes remote priority capture logic to hold task priority data indicative of a task priority of the processors while they are available for lowest priority interrupt destination arbitration (LPIDA). The system also includes lowest priority logic to perform the LPIDA to select which of the processors is to receive an interrupt message based on contents of the remote priority capture logic, the interrupt message being provided to the processor through the processor bus.
摘要翻译：本发明的一个实施例包括用于连接计算机系统的装置，例如桥。该设备包括远程优先级捕获逻辑，以保存指示可用于最低优先级中断目的地仲裁（LPIDA）的计算机系统中的每个处理器的任务优先级的任务优先级数据。该装置还包括执行LPIDA以选择计算机系统中的处理器的最低优先级逻辑是基于远程优先级捕获逻辑的内容接收中断消息。本发明的另一实施例包括具有处理器和耦合到处理器的处理器总线的多处理器系统。该系统包括远程优先级捕获逻辑，以保持指示处理器的任务优先级的任务优先级数据，同时它们可用于最低优先级中断目的地仲裁（LPIDA）。该系统还包括执行LPIDA的最低优先级逻辑，以根据远程优先级捕获逻辑的内容选择哪些处理器接收中断消息，该中断消息通过处理器总线提供给处理器。

32. 发明授权

US5923857A Method and apparatus for ordering writeback data transfers on a bus 失效
标题翻译：在总线上订购回写数据传输的方法和装置
公开(公告)号：US5923857A
公开(公告)日：1999-07-13
申请号：US708922
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
IPC分类号： G06F12/08 , G06F13/14 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method and apparatus for ordering data transfers includes an identifier of a critical portion of data being received from a requesting agent along with a request for data. Writeback data corresponding to the requested data is then transferred to the bus as a plurality of portions and ordered to ensure that a first portion which includes the critical portion of the data is transferred to the bus first.
摘要翻译：用于排序数据传输的方法和装置包括从请求代理接收的数据的关键部分的标识符以及数据请求。然后将与所请求的数据相对应的回写数据作为多个部分传送到总线，并被排序以确保包括数据的关键部分的第一部分首先被传送到总线。

33. 发明授权

US5919254A Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system 失效
标题翻译：用于在多处理系统中切换源同步和公共时钟数据传输模式的方法和装置
公开(公告)号：US5919254A
公开(公告)日：1999-07-06
申请号：US881941
申请日：1997-06-25
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , William S. Wu , Len J. Schultz
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , William S. Wu , Len J. Schultz
IPC分类号： G06F13/38 , G06F13/40 , G06F1/12 , G06F13/42
CPC分类号： G06F13/385 , G06F13/4018 , G06F13/405
摘要： A method and apparatus for transferring data between bus agents in a computer system including a bus operating at a bus clock rate. The method includes the step of receiving a transaction request from a requesting agent including an indication of a plurality of data widths the requesting agent processes. In response to the transaction request, a data transmission is configured in accordance with a data width that both the requesting agent and a responding agent process. The data transmission is performed asynchronously with respect to the bus clock if the data width is one of a first plurality of data widths, otherwise, the data transmission is performed synchronously with respect to the bus clock.
摘要翻译：一种用于在包括以总线时钟速率工作的总线的计算机系统中的总线代理之间传送数据的方法和装置。该方法包括从请求代理接收交易请求的步骤，包括请求代理处理的多个数据宽度的指示。响应于交易请求，根据请求代理和响应代理进程的数据宽度配置数据传输。如果数据宽度是第一多个数据宽度之一，则相对于总线时钟异步执行数据传输，否则，数据传输是相对于总线时钟同步执行的。

34. 发明授权

US5911053A Method and apparatus for changing data transfer widths in a computer system 失效
标题翻译：用于在计算机系统中改变数据传输宽度的方法和装置
公开(公告)号：US5911053A
公开(公告)日：1999-06-08
申请号：US723572
申请日：1996-09-30
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Gurbir Singh
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Gurbir Singh
IPC分类号： G06F13/40 , G06F3/00
CPC分类号： G06F13/4018
摘要： In a method and apparatus for changing data transfer widths in a computer system, a first agent on a bus provides a first indication to a second agent on the bus identifying one or more data transfer widths supported by the first agent. The second agent then provides a second indication to the first agent identifying one or more data transfer widths supported by the second agent. A data transfer width is then determined based on the first indication and the second indication. According to an embodiment of the present invention, a third agent involved in a transaction is also able to provide a third indication to the first and/or second agents identifying one or more data transfer widths supported by the third agent. The data transfer width(s) is then determined based on the first, second, and third indications.
摘要翻译：在用于改变计算机系统中的数据传输宽度的方法和装置中，总线上的第一代理向总线上的第二代理提供第一指示，以识别第一代理所支持的一个或多个数据传输宽度。然后，第二代理向第一代理提供识别由第二代理支持的一个或多个数据传输宽度的第二指示。然后基于第一指示和第二指示确定数据传输宽度。根据本发明的实施例，参与交易的第三代理还能够向第一代理和/或第二代理提供第三指示，以识别由第三代理支持的一个或多个数据传输宽度。然后基于第一，第二和第三指示确定数据传送宽度。

35. 发明授权

US5796977A Highly pipelined bus architecture 失效
标题翻译：高度流水线总线架构
公开(公告)号：US5796977A
公开(公告)日：1998-08-18
申请号：US688238
申请日：1996-07-29
申请人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
IPC分类号： G06F12/08 , G06F13/18 , G06F12/00 , G06F13/00
CPC分类号： G06F13/18 , G06F12/0831
摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
摘要翻译：描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

36. 发明申请

US20160117278A1 PERIPHERAL PROTOCOL NEGOTIATION 有权
标题翻译：外围协议谈判
公开(公告)号：US20160117278A1
公开(公告)日：2016-04-28
申请号：US13977822
申请日：2011-10-01
申请人： Dennis M. Bell , Stephen S. Pawlowski
发明人： Dennis M. Bell , Stephen S. Pawlowski
IPC分类号： G06F13/38 , G06F9/44 , G06F13/42
CPC分类号： G06F13/387 , G06F9/4413 , G06F13/14 , G06F13/38 , G06F13/4221
摘要： Systems and methods of operating a computing system may involve utilizing at least one of a peripheral protocol negotiation and a universal connector to determine a peripheral device protocol, and reconfiguring a computer device to accommodate that peripheral device protocol Upon such a reconfiguration, the peripheral protocol negotiation may “step aside”, and one or more subsequent communications between a host computer and the peripheral device utilizing the peripheral device protocol may start.
摘要翻译：操作计算系统的系统和方法可以包括利用外围协议协商和通用连接器中的至少一个来确定外围设备协议，以及重新配置计算机设备以适应该外围设备协议。在这种重新配置之后，外围协议协商可以“搁置”，并且可以开始使用外围设备协议的主计算机和外围设备之间的一个或多个后续通信。

37. 发明授权

US06601121B2 Quad pumped bus architecture and protocol 失效
公开(公告)号：US06601121B2
公开(公告)日：2003-07-29
申请号：US09925692
申请日：2001-08-10
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

38. 发明授权

US06557071B2 Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage 失效
标题翻译：存储器系统包括具有数据选通发生器的存储器控制器和用于使用数据选通器来访问第一和第二存储器的方法
公开(公告)号：US06557071B2
公开(公告)日：2003-04-29
申请号：US09102096
申请日：1998-06-22
申请人： Patrick F. Stolt , Stephen S. Pawlowski
发明人： Patrick F. Stolt , Stephen S. Pawlowski
IPC分类号： G06F1300
CPC分类号： G06F13/1689
摘要： A memory subsystem for a computer system includes a memory controller that has a data strobe generator. The memory subsystem further includes a Dynamic Random Access Memory (“DRAM”) array coupled to the memory controller and a data path coupled to the data strobe generator and the DRAM array. The DRAM array is separated into two DRAM sets coupled to a common output bus. Access to the DRAM array begins with access to the first DRAM set. After a first Column Address Strobe (CAS) is applied to the first DRAM set, a data strobe is asserted which causes data from the first DRAM set to be latched into the data path. On the next clock cycle after the data strobe is asserted, the data strobe and first CAS are de-asserted. A second CAS is then applied to the second DRAM set on the next clock cycle after the first CAS is de-asserted. In one embodiment, the data path includes a latch that has inputs coupled to the data strobe and an output of the DRAM array via the common output bus. In a further embodiment, the data path includes a flip-flop that has an input coupled to the latch output, and a clock input coupled to the clock.
摘要翻译：用于计算机系统的存储器子系统包括具有数据选通发生器的存储器控制器。存储器子系统还包括耦合到存储器控制器的动态随机存取存储器（“DRAM”）阵列和耦合到数据选通发生器和DRAM阵列的数据通路。 DRAM阵列被分成耦合到公共输出总线的两个DRAM组。对DRAM阵列的访问从对第一DRAM集的访问开始。在将第一列地址选通（CAS）应用于第一DRAM集合之后，断言数据选通，其使得来自第一DRAM集的数据被锁存到数据路径中。在数据选通信号有效之后的下一个时钟周期，数据选通和第一个CAS被取消置位。然后在第一个CAS被取消断言之后，第二个CAS在下一个时钟周期被应用到第二个DRAM集合。在一个实施例中，数据路径包括具有耦合到数据选通电路的输入和经由公共输出总线的DRAM阵列的输出的锁存器。在另一实施例中，数据路径包括具有耦合到锁存器输出的输入和耦合到时钟的时钟输入的触发器。

39. 发明授权

US06487655B1 Computer system formed with a processor and a system board provided with complementary initialization support 有权
标题翻译：计算机系统由处理器和系统板组成，提供互补的初始化支持
公开(公告)号：US06487655B1
公开(公告)日：2002-11-26
申请号：US09302163
申请日：1999-04-29
申请人： Frank L. Wildgrube , Stephen S. Pawlowski
发明人： Frank L. Wildgrube , Stephen S. Pawlowski
IPC分类号： G06F9445
CPC分类号： G06F9/4403
摘要： A computer system is provided with a processor and a system board. The processor includes a processor core, at least one other non-processor core electronic component and a first non-volatile memory device. Stored inside the first non-volatile memory includes first programming instructions that provide initialization support for the at least one other non-processor core electronic component of the processor. The system board includes at least one non-processor electronic component and a second non-volatile memory device. Stored inside the second non-volatile memory device includes second programming instructions that provide initialization support for the at least one non-processor electronic component of the system board. Both the first and the second programming instructions further support a cooperative initialization protocol under which the first and second programming instructions cooperate with each other to initialize the computer system at power-on/reset.
摘要翻译：计算机系统具有处理器和系统板。处理器包括处理器核心，至少一个其它非处理器核心电子部件和第一非易失性存储器件。存储在第一非易失性存储器内部包括为处理器的至少一个其他非处理器核心电子部件提供初始化支持的第一编程指令。系统板包括至少一个非处理器电子部件和第二非易失性存储器件。存储在第二非易失性存储器件内部的第二编程指令包括为系统板的至少一个非处理器电子部件提供初始化支持的第二编程指令。第一和第二编程指令进一步支持协作初始化协议，第一和第二编程指令在该合作初始化协议下彼此协作以在上电/复位时初始化计算机系统。

40. 发明授权

US06381665B2 Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals 有权
公开(公告)号：US06381665B2
公开(公告)日：2002-04-30
申请号：US09552162
申请日：2000-04-18
申请人： Stephen S. Pawlowski
发明人： Stephen S. Pawlowski
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes decode logic to receive at least some of the address signals and data signals and provide a decoded signal at one of several decode output lines of the decode logic. A redirection table includes a send pending bit that is set responsive to the decode signal. In another embodiment, an apparatus includes dedicated interrupt ports to receive an interrupt request signal. The apparatus also includes address and data ports capable of receiving an interrupt request signal in the form of address signals and data signals, and decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals. A redirection table includes a send pending bit to be set in response to either the interrupt request signal at the dedicated interrupt ports or in response to the decode signal.

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