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    • 35. 发明授权
    • Method of forming a dielectric layer pattern and method of manufacturing a non-volatile memory device using the same
    • 形成电介质层图案的方法和使用其制造非易失性存储器件的方法
    • US07727893B2
    • 2010-06-01
    • US12336863
    • 2008-12-17
    • Jae-Ho MinDong-Hyun Kim
    • Jae-Ho MinDong-Hyun Kim
    • H01L21/311
    • H01L27/115H01L21/31105H01L21/31116H01L21/31122H01L27/11521
    • In a method of forming a dielectric layer pattern, lower patterns are formed on a substrate. A first dielectric layer is formed on sidewalls and upper surfaces of the lower patterns and a surface of the substrate. A mask pattern is formed on the first dielectric layer to partially expose the first dielectric layer. The exposed first dielectric layer on upper surfaces and upper sidewalls of the lower patterns is partially removed and the removed first dielectric layer is deposited on surfaces of the first dielectric layer between the lower patterns, to form a second dielectric layer having a thickness greater than that of the first dielectric layer. The second dielectric layer on the sidewalls of the lower patterns and the substrate is etched to form a dielectric layer pattern. Accordingly, damage to the underlying layer may be reduced, and an unnecessary dielectric layer may be completely removed.
    • 在形成电介质层图案的方法中,在基板上形成下图案。 第一电介质层形成在下图案的侧壁和上表面以及基板的表面上。 在第一电介质层上形成掩模图案以部分地暴露第一介电层。 部分地去除在下图案的上表面和上侧壁上的暴露的第一电介质层,并且将去除的第一介电层沉积在下图案之间的第一介电层的表面上,以形成厚度大于其的厚度的第二电介质层。 的第一介电层。 在下图案和衬底的侧壁上的第二电介质层被蚀刻以形成电介质层图案。 因此,可能减少对下层的损伤,并且可以完全去除不需要的介电层。
    • 36. 发明申请
    • METHOD OF FORMING A DIELECTRIC LAYER PATTERN AND METHOD OF MANUFACTURING A NON-VOLATILE MEMORY DEVICE USING THE SAME
    • 形成介质层图案的方法和使用其制造非易失性存储器件的方法
    • US20090155968A1
    • 2009-06-18
    • US12336863
    • 2008-12-17
    • Jae-Ho MinDong-Hyun Kim
    • Jae-Ho MinDong-Hyun Kim
    • H01L21/336H01L21/311
    • H01L27/115H01L21/31105H01L21/31116H01L21/31122H01L27/11521
    • In a method of forming a dielectric layer pattern, lower patterns are formed on a substrate. A first dielectric layer is formed on sidewalls and upper surfaces of the lower patterns and a surface of the substrate. A mask pattern is formed on the first dielectric layer to partially expose the first dielectric layer. The exposed first dielectric layer on upper surfaces and upper sidewalls of the lower patterns is partially removed and the removed first dielectric layer is deposited on surfaces of the first dielectric layer between the lower patterns, to form a second dielectric layer having a thickness greater than that of the first dielectric layer. The second dielectric layer on the sidewalls of the lower patterns and the substrate is etched to form a dielectric layer pattern. Accordingly, damage to the underlying layer may be reduced, and an unnecessary dielectric layer may be completely removed.
    • 在形成电介质层图案的方法中,在基板上形成下图案。 第一电介质层形成在下图案的侧壁和上表面以及基板的表面上。 在第一电介质层上形成掩模图案以部分地暴露第一介电层。 部分地去除在下图案的上表面和上侧壁上的暴露的第一电介质层,并且将去除的第一介电层沉积在下图案之间的第一介电层的表面上,以形成厚度大于其的厚度的第二电介质层。 的第一介电层。 在下图案和衬底的侧壁上的第二电介质层被蚀刻以形成电介质层图案。 因此,可能减少对下层的损伤,并且可以完全去除不需要的介电层。
    • 38. 发明申请
    • METHODS OF FORMING A METAL OXIDE LAYER PATTERN HAVING A DECREASED LINE WIDTH OF A PORTION THEREOF AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
    • 形成具有其部分的下降线宽度的金属氧化物层图案的方法和使用其制造半导体器件的方法
    • US20080199975A1
    • 2008-08-21
    • US12032018
    • 2008-02-15
    • Min-Joon ParkChang-Jin KangDong-Hyun Kim
    • Min-Joon ParkChang-Jin KangDong-Hyun Kim
    • H01L21/18H01L21/3065
    • H01L27/11521H01L21/0206H01L21/31116H01L21/31122H01L21/32136H01L27/115H01L27/11502H01L27/11507H01L28/55H01L29/40117
    • Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer. The present invention also provides methods of manufacturing a semiconductor device including forming a metal oxide layer and a first conductive layer on a substrate; etching the metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increase in a vertically downward direction; etching the first conductive layer to provide a first conductive layer pattern; and etching the preliminary metal oxide layer pattern to provide a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer pattern.
    • 本文提供了在衬底上形成金属氧化物层图案的方法,包括在衬底上提供初步金属氧化物层; 蚀刻初始金属氧化物层以提供初步金属氧化物层图案,其中预备金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 并且以使得预备金属氧化物层的下部的线宽减小的方式蚀刻初步金属氧化物层图案以形成金属氧化物层图案。 本发明还提供了制造半导体器件的方法,包括在衬底上形成金属氧化物层和第一导电层; 蚀刻金属氧化物层以提供初步金属氧化物层图案,其中初始金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 蚀刻第一导电层以提供第一导电层图案; 并且蚀刻初步金属氧化物层图案以提供金属氧化物层图案,以便减小初步金属氧化物层图案的下部的线宽度。
    • 39. 发明申请
    • Non-volatile memory devices and methods of manufacturing the same
    • 非易失性存储器件及其制造方法
    • US20080150008A1
    • 2008-06-26
    • US12004985
    • 2007-12-21
    • Dong-Hyun KimChang-Jin Kang
    • Dong-Hyun KimChang-Jin Kang
    • H01L29/792H01L21/28
    • H01L21/28282
    • Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.
    • 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层,隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。
    • 40. 发明申请
    • Plasma display panel
    • 等离子显示面板
    • US20070120490A1
    • 2007-05-31
    • US11604548
    • 2006-11-27
    • Dong-Hyun Kim
    • Dong-Hyun Kim
    • H01J17/02
    • H01J11/38H01J11/12H01J2211/245
    • Provided is a plasma display panel that includes a first substrate, a second substrate facing the first substrate, a pair of discharge electrode lines which are disposed between the first substrate and the second substrate and comprise a first discharge electrode line formed by connecting a plurality of sub-electrode lines and a second discharge electrode line that faces the first discharge electrode line and is formed by connecting a plurality of sub-electrode lines, and dielectric layers that bury the discharge electrode lines. Since the dielectric layers include B2O3 and BaO, yellowness caused by the migration of a metal component included in the discharge electrode lines into the dielectric layers during a firing process can be prevented.
    • 提供了一种等离子体显示面板,其包括第一基板,面向第一基板的第二基板,一对放电电极线,设置在第一基板和第二基板之间,并且包括通过连接多个 子电极线和与第一放电电极线相对并且通过连接多个子电极线而形成的第二放电电极线以及掩埋放电电极线的电介质层。 由于介电层包括B 2 O 3和BaO,在烧制过程中由包含在放电电极线中的金属成分迁移到电介质层中引起的黄色可以 被阻止