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31. 发明授权

US06605981B2 Apparatus for biasing ultra-low voltage logic circuits 有权
公开(公告)号：US06605981B2
公开(公告)日：2003-08-12
申请号：US09842544
申请日：2001-04-26
申请人： Andres Bryant , Peter Edwin Cottrell , John Joseph Ellis-Monaghan , Mark B. Ketchen , Edward Joseph Nowak
发明人： Andres Bryant , Peter Edwin Cottrell , John Joseph Ellis-Monaghan , Mark B. Ketchen , Edward Joseph Nowak
IPC分类号： G05F302
CPC分类号： G05F3/205 , H01L27/0218
摘要： An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.

32. 发明授权

US06459106B2 Dynamic threshold voltage devices with low gate to substrate resistance 有权
标题翻译：动态门限电压器件具有低栅极到衬底电阻
公开(公告)号：US06459106B2
公开(公告)日：2002-10-01
申请号：US09753521
申请日：2001-01-03
申请人： Andres A. Bryant , Edward Joseph Nowak , Minh Ho Tong
发明人： Andres A. Bryant , Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H01L29768
CPC分类号： H01L21/84 , H01L29/78609 , H01L29/78612
摘要： Described is a dynamic threshold field effect transistor (DTFET) that includes a gate-to-body contact structure within the gate. By forming the gate-to-body contact structure that can reduce the gate-to-body contact resistance and increase the device packing density, the DTFET can be used in silicon on insulator (SOI) technologies and take full advantages of the DT-CMOS performance benefit.
摘要翻译：描述了一种动态阈值场效应晶体管（DTFET），其包括栅极内的栅对体接触结构。通过形成能够降低栅对体接触电阻并增加器件封装密度的栅对体接触结构，DTFET可用于绝缘体上硅（SOI）技术，并充分利用了DT-CMOS 性能优势。

33. 发明授权

US06191451B1 Semiconductor device with decoupling capacitance 失效
标题翻译：具有去耦电容的半导体器件
公开(公告)号：US06191451B1
公开(公告)日：2001-02-20
申请号：US09016026
申请日：1998-01-30
申请人： Edward Joseph Nowak , Minh Ho Tong
发明人： Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L27/0248 , H01L27/088
摘要： A semiconductor device is disclosed that provides a decoupling capacitance and method for the same. The semiconductor device includes a first circuit region having a first device layer over an isolation layer and a second circuit region adjacent the first circuit region having a second device layer over a well. An implant layer is implanted beneath the isolation layer in the first circuit region, which will connect to the well of the second circuit region.
摘要翻译：公开了提供一种去耦电容的半导体器件及其方法。半导体器件包括具有在隔离层上的第一器件层的第一电路区域和与第一电路区域相邻的第二电路区域，该第二电路区域在阱上具有第二器件层。在第一电路区域中的隔离层下方植入注入层，其将连接到第二电路区域的阱。

34. 发明授权

US5672994A Antifuse circuit using standard MOSFET devices 失效
标题翻译：防漏电路采用标准MOSFET器件
公开(公告)号：US5672994A
公开(公告)日：1997-09-30
申请号：US576026
申请日：1995-12-21
申请人： Wai-Ming William Au , Edward Joseph Nowak , Minh Ho Tong
发明人： Wai-Ming William Au , Edward Joseph Nowak , Minh Ho Tong
IPC分类号： G11C17/16 , H01L23/525 , H01H37/76
CPC分类号： G11C17/16 , H01L23/5252 , H01L2924/0002
摘要： A programmable device is formed from a field-effect transistor. Specifically, the present invention generally related to integrated circuit (IC) structures and more particularly, to an improved antifuse structure for use in programming redundant and customizable IC chips. The anti-fuse is NFET made of MOS material and formed at a face of a semiconductor layer having an n-type doped source, and drain region, and a p-type doped channel region separating the source and drain regions. The device is programmed by applying a high voltage to the NFET drain to form a hot spot located along the channel width of the drain and thereby forming a bridge, which now has less resistance than the surrounding channel material, to the NFET source.
摘要翻译：可编程器件由场效应晶体管形成。具体地，本发明一般涉及集成电路（IC）结构，更具体地说，涉及用于编程冗余且可定制的IC芯片的改进的反熔丝结构。反熔丝是由MOS材料制成的NFET，并且形成在具有n型掺杂源的半导体层的表面和漏极区域以及分离源极和漏极区域的p型掺杂沟道区域。通过向NFET漏极施加高电压来形成器件，以形成沿着漏极的沟道宽度定位的热点，从而形成现在具有比周围通道材料更小的电阻到NFET源的桥。

35. 发明授权

US5670388A Method of making contacted body silicon-on-insulator field effect transistor 失效
标题翻译：制造接触体绝缘体上的场效应晶体管的方法
公开(公告)号：US5670388A
公开(公告)日：1997-09-23
申请号：US542592
申请日：1995-10-13
申请人： Brian John Machesney , Jack Allan Mandelman , Edward Joseph Nowak
发明人： Brian John Machesney , Jack Allan Mandelman , Edward Joseph Nowak
IPC分类号： H01L29/786 , H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L2924/0002 , Y10S148/15 , Y10S438/98
摘要： Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.
摘要翻译：提出了用于形成用于SOI FET的体衬底连接器的结构和方法。该连接器在不干扰源极和漏极的装置的一侧基本上与栅极导体共同对准。因此，本体保持靠近基底电位，并且连接器为多数载体快速离开身体提供了路径。通过以不扰乱由栅极成像的电荷的方式接触SOI MOSFET器件的主体，消除寄生双极效应，同时保持SOI MOSFET器件的期望属性，例如低衬底偏置灵敏度和陡峭的次阈值斜率。通过形成与栅极导体基本上共同对准的连接器，连接使用很少或没有表面积。

36. 发明授权

US08518757B2 Method of fabricating strained semiconductor structures from silicon-on-insulator (SOI) 有权
标题翻译：从绝缘体上硅（SOI）制造应变半导体结构的方法
公开(公告)号：US08518757B2
公开(公告)日：2013-08-27
申请号：US12707975
申请日：2010-02-18
申请人： Brent Alan Anderson , Edward Joseph Nowak
发明人： Brent Alan Anderson , Edward Joseph Nowak
IPC分类号： H01L21/00 , H01L21/84 , H01L21/338 , H01L21/336 , H01L21/36 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/0649 , H01L29/4238 , H01L29/7842 , H01L29/7848 , H01L29/7849 , H01L29/785
摘要： A strained semiconductor structure and method of making the structure. The method includes: forming a pad layer on a top surface of a silicon layer of a substrate, the substrate comprising the silicon layer separated from a supporting substrate by a buried oxide layer; forming openings in the pad layer and etching trenches through the silicon layer to the buried oxide layer in the openings to form silicon regions from the silicon layer; forming spacers on the entirety of sidewalls of the silicon regions exposed in the trenches; forming oxide regions in corners of the silicon regions proximate to both the sidewalls and the buried oxide layer to form strained silicon regions, the oxide regions not extending to the pad layer; and removing at least a portion of the spacers and filling remaining spaces in the trenches with silicon to form filled regions abutting the strained silicon region.
摘要翻译：一种应变半导体结构及其制造方法。该方法包括：在衬底的硅层的顶表面上形成焊盘层，所述衬底包括通过掩埋氧化物层从支撑衬底分离的硅层; 在所述焊盘层中形成开口并且蚀刻通过所述硅层的沟槽到所述开口中的所述掩埋氧化物层，以从所述硅层形成硅区域; 在暴露在沟槽中的硅区域的整个侧壁上形成间隔物; 在接近两个侧壁和掩埋氧化物层的硅区域的角落中形成氧化物区域，以形成应变硅区域，氧化物区域不延伸到焊盘层; 并且移除至少一部分间隔物并用硅填充沟槽中的剩余空间以形成邻近应变硅区的填充区。

37. 发明授权

US08039376B2 Methods of changing threshold voltages of semiconductor transistors by ion implantation 有权
标题翻译：通过离子注入来改变半导体晶体管的阈值电压的方法
公开(公告)号：US08039376B2
公开(公告)日：2011-10-18
申请号：US11939578
申请日：2007-11-14
申请人： William F. Clark, Jr. , Edward Joseph Nowak
发明人： William F. Clark, Jr. , Edward Joseph Nowak
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L21/823431 , H01L29/105 , H01L29/66795 , H01L29/66803
摘要： A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) a semiconductor body region. The method further includes implanting an adjustment dose of dopants of a first doping polarity into the semiconductor body region by an adjustment implantation process. Ion bombardment of the adjustment implantation process is in the reference direction. The method further includes (i) patterning the semiconductor substrate resulting in side walls of the semiconductor body region being exposed to a surrounding ambient and then (ii) implanting a base dose of dopants of a second doping polarity into the semiconductor body region by a base implantation process. Ion bombardment of the base implantation process is in a direction which makes a non-zero angle with the reference direction.
摘要翻译：一种形成半导体结构的方法。该方法包括提供包括半导体衬底的半导体结构。半导体衬底包括（i）限定垂直于顶部衬底表面的参考方向的顶部衬底表面和（ii）半导体本体区域。该方法还包括通过调整注入工艺将第一掺杂极性的掺杂剂的调整剂量注入到半导体体区域中。离子轰击调整植入过程在参考方向。该方法还包括（i）对半导体衬底进行图形化，导致半导体体区域的侧壁暴露于周围环境，然后（ii）将碱性剂量的第二掺杂极性掺杂剂注入到半导体本体区域中，植入过程。基极注入工艺的离子轰击在与参考方向成非零角度的方向上。

38. 发明申请

US20110198695A1 Strained Semiconductor Structures and Method of Fabricating Strained Semiconductor Structures 有权
标题翻译：应变半导体结构和制造应变半导体结构的方法
公开(公告)号：US20110198695A1
公开(公告)日：2011-08-18
申请号：US12707975
申请日：2010-02-18
申请人： Brent Alan Anderson , Edward Joseph Nowak
发明人： Brent Alan Anderson , Edward Joseph Nowak
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/0649 , H01L29/4238 , H01L29/7842 , H01L29/7848 , H01L29/7849 , H01L29/785
摘要： A strained semiconductor structure and method of making the structure. The method includes: forming a pad layer on a top surface of a silicon layer of a substrate, the substrate comprising the silicon layer separated from a supporting substrate by a buried oxide layer; forming openings in the pad layer and etching trenches through the silicon layer to the buried oxide layer in the openings to form silicon regions from the silicon layer; forming spacers on the entirety of sidewalls of the silicon regions exposed in the trenches; forming oxide regions in corners of the silicon regions proximate to both the sidewalls and the buried oxide layer to form strained silicon regions, the oxide regions not extending to the pad layer; and removing at least a portion of the spacers and filling remaining spaces in the trenches with silicon to form filled regions abutting the strained silicon region.
摘要翻译：一种应变半导体结构及其制造方法。该方法包括：在衬底的硅层的顶表面上形成焊盘层，所述衬底包括通过掩埋氧化物层从支撑衬底分离的硅层; 在所述焊盘层中形成开口并且蚀刻通过所述硅层的沟槽到所述开口中的所述掩埋氧化物层，以从所述硅层形成硅区域; 在暴露在沟槽中的硅区域的整个侧壁上形成间隔物; 在接近两个侧壁和掩埋氧化物层的硅区域的角落中形成氧化物区域，以形成应变硅区域，氧化物区域不延伸到焊盘层; 并且移除至少一部分间隔物并用硅填充沟槽中的剩余空间以形成邻近应变硅区的填充区。

39. 发明授权

US07851315B2 Method for fabricating a field effect transistor having a dual thickness gate electrode 有权
标题翻译：制造具有双厚度栅电极的场效应晶体管的方法
公开(公告)号：US07851315B2
公开(公告)日：2010-12-14
申请号：US12037113
申请日：2008-02-26
申请人： Brent Alan Anderson , Andres Bryant , William F. Clark, Jr. , Edward Joseph Nowak
发明人： Brent Alan Anderson , Andres Bryant , William F. Clark, Jr. , Edward Joseph Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
摘要翻译：场效应晶体管和制造场效应晶体管的方法。场效应晶体管包括：硅体，硅体的周边抵靠电介质隔离; 源体和漏极，其形成在主体中并形成在主体中的通道的相对侧上; 以及位于主体和导电栅电极之间的栅极电介质层，栅极电介质层的与表面主体直接物理接触的底表面和栅电极与所述栅极电介质层，所述栅电极具有第一厚度的第一区域和具有第二厚度的第二区域，所述第一区域沿着所述沟道区域上的所述栅极电介质层的顶表面延伸，所述第二厚度大于所述第一厚度厚度。

40. 发明授权

US07821109B2 Stressed dielectric devices and methods of fabricating same 失效
标题翻译：电介质器件及其制造方法
公开(公告)号：US07821109B2
公开(公告)日：2010-10-26
申请号：US12570045
申请日：2009-09-30
申请人： Brent Alan Anderson , Edward Joseph Nowak
发明人： Brent Alan Anderson , Edward Joseph Nowak
IPC分类号： H01L23/58
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76832 , H01L29/7843
摘要： A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.
摘要翻译：制作结构的结构和方法。该结构包括场效应晶体管，包括：形成在硅衬底中的第一和第二源极/漏极，第一和第二源极/漏极间隔开并由衬底中的沟道区分隔开; 位于所述沟道区上的所述衬底顶表面上的栅电介质; 以及在所述栅极电介质的顶表面上的导电栅极; 以及栅极上的第一介电材料的介电柱; 以及介于第一和第二源极/漏极之间的第二介电材料的电介质层，介电柱的侧壁与电介质层直接物理接触，该介电柱不具有内部应力或不同于内部应力的内部应力电介质层。

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