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    • 36. 发明授权
    • System and method for improving a data redundancy scheme in a solid state subsystem with additional metadata
    • 用于通过附加元数据改进固态子系统中的数据冗余方案的系统和方法
    • US08700951B1
    • 2014-04-15
    • US13044400
    • 2011-03-09
    • Matthew CallJohn A. MorrisonLan D. PhanMei-Man L. Syu
    • Matthew CallJohn A. MorrisonLan D. PhanMei-Man L. Syu
    • G06F11/08
    • G06F11/108G06F11/0727G06F11/0751G06F11/1441G06F2211/104
    • In one embodiment of the invention, a flash-based/solid-state storage system with an implemented data redundancy scheme such as RAID is configured to hold parity data in a volatile memory such as RAM and write such parity data to the non-volatile flash media when a full stripe of data has been written to the media. Other embodiments in certain situations force an early write of the parity for a partial stripe that has not been fully written to the non-volatile media. Those situations may include a data access error on data in a partial stripe and a detected power loss event with a partial stripe present. Embodiments are directed to writing additional data with the parity data for the partial stripe and then later using the additional data in data recovery. This approach allows the controller to easily detect the presence of a partial stripe and handle such a stripe accordingly.
    • 在本发明的一个实施例中,具有诸如RAID的实现的数据冗余方案的基于闪存的/固态存储系统被配置为将奇偶校验数据保存在诸如RAM的易失性存储器中,并将这种奇偶校验数据写入非易失性闪存 当已将完整的数据条带写入媒体时,媒体。 在某些情况下的其他实施例迫使尚未完全写入非易失性介质的部分条纹的奇偶校验的早期写入。 这些情况可能包括部分条带中数据的数据访问错误和带有部分条带的检测到的功率损失事件。 实施例涉及用部分条带的奇偶校验数据写入附加数据,然后再用数据恢复中的附加数据。 这种方法允许控制器容易地检测部分条纹的存在并相应地处理这样的条带。
    • 39. 发明授权
    • Trap mode register
    • 陷阱模式寄存器
    • US07480755B2
    • 2009-01-20
    • US11006964
    • 2004-12-08
    • Russ HerrellGerald J. Kaufman, Jr.John A. Morrison
    • Russ HerrellGerald J. Kaufman, Jr.John A. Morrison
    • G06F13/24
    • G06F13/24
    • Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.
    • 描述了与配置有陷阱模式寄存器,多个中断向量地址寄存器和多个中断向量表的系统相关联的系统,方法,介质和其他实施例。 一个示例性系统实施例包括用于初始化陷阱模式寄存器的逻辑,用于初始化中断向量地址寄存器以及用于初始化中断向量表。 当在配置有示例性系统的计算机中发生陷阱时,陷阱模式寄存器可以例如基于陷阱类型或陷阱数据来选择相关联的中断向量地址寄存器,以通过以下方式提供中断向量表的地址 可以调用陷阱处理程序。