专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US09582275B2 Method and apparatus for obtaining a call stack to an event of interest and analyzing the same 有权
标题翻译：用于获得对感兴趣的事件的调用栈的分析的方法和装置
公开(公告)号：US09582275B2
公开(公告)日：2017-02-28
申请号：US13118766
申请日：2011-05-31
申请人： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
发明人： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30 , G06F11/34
CPC分类号： G06F9/30058 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/3016 , G06F11/3409 , G06F11/3476 , G06F11/348 , G06F12/0875
摘要： In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括性能监视器，其包括最后一个分支记录（LBR）堆栈，以将呼叫堆栈存储到感兴趣的事件，响应于该事件的触发来收集呼叫栈。处理器还包括控制LBR堆栈以调用堆栈模式操作的逻辑，使得从叶片功能返回时清除叶子功能的调用指令的条目。描述和要求保护其他实施例。

32. 发明授权

US09092214B2 SIMD processor with programmable counters externally configured to count executed instructions having operands of particular register size and element size combination 有权
标题翻译：具有可编程计数器的SIMD处理器，其外部配置为对具有特定寄存器大小和元件大小组合的操作数的执行指令进行计数
公开(公告)号：US09092214B2
公开(公告)日：2015-07-28
申请号：US13434564
申请日：2012-03-29
申请人： Laura A. Knauth , Matthew C. Merten , Ronak Singhal , Hugh M. Caffey
发明人： Laura A. Knauth , Matthew C. Merten , Ronak Singhal , Hugh M. Caffey
IPC分类号： G06F15/80 , G06F9/30 , G06F11/34
CPC分类号： G06F9/3013 , G06F9/30109 , G06F9/30112 , G06F11/3409 , G06F11/3466 , G06F2201/88
摘要： A processor includes an execution unit to execute instructions, where each operand of each executed instruction has one or more elements of an element size and at least one operand of the instruction corresponds to a register of a register size. The processor further includes a counter configured to count a number of instructions that have been executed by the execution unit associated with a particular combination of register size and element size.
摘要翻译：处理器包括执行指令的执行单元，其中每个执行指令的每个操作数具有元素大小的一个或多个元素，并且指令的至少一个操作数对应于寄存器大小的寄存器。处理器还包括计数器，其被配置为对由执行单元执行的与寄存器大小和元素大小的特定组合相关联的指令数进行计数。

33. 发明申请

US20140156977A1 ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
标题翻译：启用和禁用分支机构错误预测的第二个执行单位
公开(公告)号：US20140156977A1
公开(公告)日：2014-06-05
申请号：US13994699
申请日：2011-12-28
申请人： Mark J. Dechene , Matthew C. Merten , Sean P. Mirkes
发明人： Mark J. Dechene , Matthew C. Merten , Sean P. Mirkes
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/3844 , G06F9/3851 , G06F9/3885
摘要： Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.
摘要翻译：描述了在微处理器中启用和/或禁用辅助跳转执行单元（JEU）的技术。次级JEU被并入微处理器以与主JEU同时操作，并且能够在多个分支上处理同时的分支错误预测。次级JEU的激活和停用可以由压力计数器或置信计数器来控制。压力计数器机构增加在处理器内执行的每个分支操作的计数，并在每个周期期间将计数减去衰减值。置信度计数机制增加每个正确预测分支的计数，并减少每个错误预测的计数。当计数器超过激活阈值时，每个计数器发出一个激活组件，例如端口绑定硬件组件，开始将微操作绑定到辅助JEU。计数器机制可能是线程不可知或线程特定的。

34. 发明申请

US20140013086A1 ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS 审中-公开
标题翻译：附加说明与独立的携带链
公开(公告)号：US20140013086A1
公开(公告)日：2014-01-09
申请号：US13993483
申请日：2011-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30094 , G06F9/3838
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.
摘要翻译：提供了彼此之间没有数据依赖性的多个附加指令。第一加法指令将其进位输出存储在标志寄存器的第一标志中，而不修改标志寄存器中的第二标志。第二加法指令将其进位输出存储在标志寄存器的第二标志中，而不修改标志寄存器中的第一个标志。

35. 发明授权

US08560781B2 Technique for using memory attributes 有权
标题翻译：使用内存属性的技术
公开(公告)号：US08560781B2
公开(公告)日：2013-10-15
申请号：US13175928
申请日：2011-07-04
申请人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saba , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
发明人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saba , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：一种使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

36. 发明申请

US20130232499A1 COMPARE AND EXCHANGE OPERATION USING SLEEP-WAKEUP MECHANISM 审中-公开
标题翻译：使用睡眠唤醒机制的比较和交换操作
公开(公告)号：US20130232499A1
公开(公告)日：2013-09-05
申请号：US13843305
申请日：2013-03-15
申请人： Bratin Saha , Matthew C. Merten , Per Hammarlund
发明人： Bratin Saha , Matthew C. Merten , Per Hammarlund
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/3857 , G06F9/526 , G06F2209/521
摘要： A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.
摘要翻译：提供了一种使用睡眠 - 唤醒机制执行比较和交换操作的方法，装置和系统。根据一个实施例，执行处理器处的指令以帮助代表处理器获取锁定。如果锁不能由处理器获取，则指令将进入休眠状态，直到发生事件为止。

37. 发明申请

US20120311307A1 Method And Apparatus For Obtaining A Call Stack To An Event Of Interest And Analyzing The Same 有权
标题翻译：方法和设备获取一个调用堆栈到一个有趣的事件和分析它
公开(公告)号：US20120311307A1
公开(公告)日：2012-12-06
申请号：US13118766
申请日：2011-05-31
申请人： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
发明人： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/3016 , G06F11/3409 , G06F11/3476 , G06F11/348 , G06F12/0875
摘要： In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括性能监视器，其包括最后一个分支记录（LBR）堆栈，以将呼叫堆栈存储到感兴趣的事件，响应于该事件的触发来收集呼叫栈。处理器还包括控制LBR堆栈以调用堆栈模式操作的逻辑，使得从叶片功能返回时清除叶子功能的调用指令的条目。描述和要求保护其他实施例。

38. 发明授权

US07991965B2 Technique for using memory attributes 有权
标题翻译：使用内存属性的技术
公开(公告)号：US07991965B2
公开(公告)日：2011-08-02
申请号：US11349661
申请日：2006-02-07
申请人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saha , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
发明人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saha , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
IPC分类号： G06F13/376
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

39. 发明授权

US07529914B2 Method and apparatus for speculative execution of uncontended lock instructions 有权
标题翻译：用于推测执行无限制锁定指令的方法和装置
公开(公告)号：US07529914B2
公开(公告)日：2009-05-05
申请号：US10883519
申请日：2004-06-30
申请人： Bratin Saha , Matthew C. Merten , Per Hammarlund
发明人： Bratin Saha , Matthew C. Merten , Per Hammarlund
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3842
摘要： A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.
摘要翻译：公开了一种用于在乱序处理器中推测地执行锁定指令的方法和装置。在一个实施例中，预先确定给定的锁定指令是否将被实际竞争。如果不是，则锁定指令可以被视为具有可以推测地执行的正常负载微操作。监视器逻辑可能会查找锁定指令实际上有争议的迹象。如果没有发现这样的指示，则与锁定指令相对应的投机负载微操作和其他微操作可能会退出。然而，如果事实上发现这样的指示，则可以重新启动锁定指令，并且可以更新预测机制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式