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31. 发明申请

US20070040577A1 Apparatus and methods for optimizing the performance of programmable logic devices 有权
标题翻译：用于优化可编程逻辑器件性能的装置和方法
公开(公告)号：US20070040577A1
公开(公告)日：2007-02-22
申请号：US11204570
申请日：2005-08-16
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： H03K19/177
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

32. 发明授权

US08823586B2 Method and system for GNSS assistance data or LTO data download over a broadcast band 有权
标题翻译：通过广播频段下载GNSS辅助数据或LTO数据下载的方法和系统
公开(公告)号：US08823586B2
公开(公告)日：2014-09-02
申请号：US12394152
申请日：2009-02-27
申请人： Steven Malkos , Christopher Lane
发明人： Steven Malkos , Christopher Lane
IPC分类号： G01S19/05
CPC分类号： G01S19/39 , G01S19/05 , G01S19/35
摘要： A combined GNSS and FM receiver receives FM signals comprising satellite navigation data from an AGNSS server. Associated navigation information such as a position fix is determined based on the received satellite navigation data. The received satellite navigation data are GNSS assistance data or LTO data. The AGNSS server generates the satellite navigation data by acquiring GNSS data from a satellite reference network. The acquired GNSS data comprise, for example, GPS data, GLONASS data and/or GALILEO data. The generated satellite navigation data are broadcasted as FM signals through RDS and/or RBDS to the combined GNSS and FM receiver. The combined GNSS and FM receiver receives updated satellite navigation data in subsequent FM signals, periodically or aperiodically, and updates associated navigation information, accordingly. The combined GNSS and FM receiver decodes the received FM radio signals for the updated satellite navigation data generated at the AGNSS server before being transmitted.
摘要翻译：组合的GNSS和FM接收器接收包括来自AGNSS服务器的卫星导航数据的FM信号。基于接收到的卫星导航数据来确定诸如位置锁定的相关导航信息。接收到的卫星导航数据是GNSS辅助数据或LTO数据。 AGNSS服务器通过从卫星参考网络获取GNSS数据来生成卫星导航数据。所获取的GNSS数据包括例如GPS数据，GLONASS数据和/或GALILEO数据。生成的卫星导航数据通过RDS和/或RBDS作为FM信号广播到组合的GNSS和FM接收机。组合的GNSS和FM接收机在周期性或不定期地接收后续FM信号中的更新的卫星导航数据，并相应地更新相关的导航信息。组合的GNSS和FM接收机解码所接收的FM无线电信号，以便在发送之前在AGNSS服务器处生成的更新的卫星导航数据。

33. 发明授权

US08407649B2 PLD architecture for flexible placement of IP function blocks 有权
公开(公告)号：US08407649B2
公开(公告)日：2013-03-26
申请号：US13468928
申请日：2012-05-10
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Christopher Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Christopher Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： G06F17/50 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

34. 发明申请

US20120217998A1 PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS 有权
标题翻译：用于柔性布置IP功能块的PLD架构
公开(公告)号：US20120217998A1
公开(公告)日：2012-08-30
申请号：US13468928
申请日：2012-05-10
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Christopher Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Christopher Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译：根据本发明的一个方面，通过中断LE阵列基本信号路由体系结构，在PLD的LE阵列内形成一个孔，使得留下用于IP功能块的孔。提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。

35. 发明授权

US08195491B2 Determining relative performance 有权
标题翻译：确定相对性能
公开(公告)号：US08195491B2
公开(公告)日：2012-06-05
申请号：US12537745
申请日：2009-08-07
申请人： Lisa H. Neuberger , Timothy P. Rogers , Greg Wilkinson , Greg Beales , Jonathan Garbutt , Nicholas Martin Stevens , George F. Chaplin , Fiona Sharples , Sajaad Jetha , Nicholas Marren , Thomas P. Leary , Mark Younger , Emma Jones , Christopher Lane
发明人： Lisa H. Neuberger , Timothy P. Rogers , Greg Wilkinson , Greg Beales , Jonathan Garbutt , Nicholas Martin Stevens , George F. Chaplin , Fiona Sharples , Sajaad Jetha , Nicholas Marren , Thomas P. Leary , Mark Younger , Emma Jones , Christopher Lane
IPC分类号： G06Q10/00
CPC分类号： G06Q10/10 , G06Q10/063 , G06Q10/0639 , G06Q30/0201 , G06Q30/0282
摘要： A method and system for evaluating a public sector organization includes identifying at least one outcome measure and at least one cost-effectiveness measure for a public sector organization; obtaining measurements associated with the measure; and determining a relative public performance measure of the public sector organization based on the measurements.
摘要翻译：用于评估公共部门组织的方法和系统包括为公共部门组织确定至少一个结果测量和至少一个成本效益测量; 获得与测量相关的测量; 并基于测量确定公共部门组织的相对公共绩效指标。

36. 发明申请

US20120089958A1 Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices 审中-公开
标题翻译：用于优化可编程逻辑器件性能的装置和方法
公开(公告)号：US20120089958A1
公开(公告)日：2012-04-12
申请号：US13326082
申请日：2011-12-14
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

37. 发明授权

US08103975B2 Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage 有权
标题翻译：使用多电源电压优化可编程逻辑器件的性能的装置和方法
公开(公告)号：US08103975B2
公开(公告)日：2012-01-24
申请号：US12165664
申请日：2008-07-01
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

38. 发明申请

US20070093071A1 Method and apparatus for processing a wafer 审中-公开
标题翻译：用于处理晶片的方法和装置
公开(公告)号：US20070093071A1
公开(公告)日：2007-04-26
申请号：US11605584
申请日：2006-11-27
申请人： Steven Verhaverbeke , J Truman , Christopher Lane , Sasson Somekh
发明人： Steven Verhaverbeke , J Truman , Christopher Lane , Sasson Somekh
IPC分类号： H01L21/465
CPC分类号： H01L21/67207 , G03F7/16 , H01L21/67115 , H01L21/67161 , H01L21/67173 , H01L21/67184 , H01L21/6719 , Y10S414/135 , Y10S414/141 , Y10S438/905
摘要： A method of a single wafer wet/dry cleaning apparatus comprising: a transfer chamber having a wafer handler contained therein; a first single wafer wet cleaning chamber directly coupled to the transfer chamber; and a first single wafer ashing chamber directly coupled to the transfer chamber.
摘要翻译：一种单晶片湿式/干式清洗设备的方法，包括：一个传送室，其中包含一个晶片处理器; 直接耦合到传送室的第一单晶片湿清洁室; 以及直接耦合到传送室的第一单个晶片灰化室。

39. 发明申请

US20070040576A1 Apparatus and methods for power management in integrated circuits 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US20070040576A1
公开(公告)日：2007-02-22
申请号：US11316390
申请日：2005-12-22
申请人： David Lewis , Christopher Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Wong , Andy Lee
发明人： David Lewis , Christopher Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Wong , Andy Lee
IPC分类号： H03K19/177
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

40. 发明申请

US20060158220A1 Methods of reducing power in programmable logic devices using low voltage swing for routing signals 有权
公开(公告)号：US20060158220A1
公开(公告)日：2006-07-20
申请号：US11039272
申请日：2005-01-19
申请人： Christopher Lane , Vikram Santurkar
发明人： Christopher Lane , Vikram Santurkar
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/0013 , H03K19/17784
摘要： Reduced voltage swing signal path circuitry is provided that lowers the internal signaling power consumption of the interconnection resources of a programmable logic device. The reduced voltage swing signal path circuitry includes a reversed routing driver circuitry to limit the voltage range of the output signal of the driver circuitry.

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