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31. 发明授权

US08479066B2 Process for making an electric testing of electronic devices 有权
标题翻译：进行电子设备电气测试的过程
公开(公告)号：US08479066B2
公开(公告)日：2013-07-02
申请号：US13027617
申请日：2011-02-15
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/28
CPC分类号： G01R31/31908 , G01R31/3025 , G01R31/318572 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/73265 , H01L2924/13091 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A process for electrically testing electronic devices includes connecting at least one electronic device to an automatic testing apparatus suitable for testing digital circuits, and sending, through the apparatus, control signals for electrically testing the electronic device. The process further includes electrically testing the electronic device through at least one reconfigurable digital interface connected to the apparatus through a dedicated digital communication channel and comprising a limited number of communication or connection lines strictly appointed to the exchange of the testing information. Response messages are sent from the electronic device to the apparatus through the digital communication channel in response to the control signals. The response messages contain mesaurements, failure information, and data.
摘要翻译：用于电测试电子设备的过程包括将至少一个电子设备连接到适合于测试数字电路的自动测试设备，以及通过设备发送用于电测试电子设备的控制信号。该方法还包括通过至少一个通过专用数字通信信道连接到该设备的可重新配置数字接口电测试电子设备，并且包括严格指定用于测试信息交换的有限数量的通信或连接线。响应于控制信号，响应消息通过数字通信信道从电子设备发送到设备。响应消息包含mesaurements，故障信息和数据。

32. 发明申请

US20110254580A1 METHOD FOR AN IMPROVED CHECKING OF REPEATABILITY AND REPRODUCIBILITY OF A MEASURING CHAIN FOR SEMICONDUCTOR DEVICE TESTING 有权
标题翻译：用于半导体器件测试的测量链的可重复性和可重复性的改进方法
公开(公告)号：US20110254580A1
公开(公告)日：2011-10-20
申请号：US13092772
申请日：2011-04-22
申请人： Sergio Tenucci , Alberto Pagani , Marco Spinetta , Bernard Ranchoux
发明人： Sergio Tenucci , Alberto Pagani , Marco Spinetta , Bernard Ranchoux
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： G05B19/41875 , G01R31/2894 , Y02P90/22 , Y02P90/86
摘要： A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.
摘要翻译：一种方法提供了对测量链的重复性和再现性的改进的检查，特别是通过半导体器件测试的质量控制。该方法包括对通过测量系统进行测量或控制的多个和不同设备提供的测试步骤，所述测量系统包括测试装置（ATE）和要进行测量或控制的每个设备之间的至少一个测量单元链。有利地，该方法包括检查构成测量链的一部分的每种类型的单元的重复性和再现性，并且在检查之后，使各种测量链之间的相关性作为整体来检查重复性和再现性，使用受到测量或控制。

33. 发明授权

US07915908B2 Crosstalk suppression in wireless testing of semiconductor devices 有权
标题翻译：半导体器件无线测试中的串扰抑制
公开(公告)号：US07915908B2
公开(公告)日：2011-03-29
申请号：US12037319
申请日：2008-02-26
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2851 , G01R31/2886 , G01R31/3025 , G01R31/303 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.
摘要翻译：一种集成在半导体材料裸片上并适于至少部分地被无线测试的集成电路，其中用于设置用于集成电路的无线测试的所选无线电通信频率的电路集成在半导体材料裸片上。

34. 发明授权

US09097637B2 Integrated electronic device for monitoring parameters within a solid structure and monitoring system using such a device 有权
标题翻译：集成电子设备，用于监测实体结构中的参数和使用这种设备的监控系统
公开(公告)号：US09097637B2
公开(公告)日：2015-08-04
申请号：US13996259
申请日：2011-10-20
申请人： Alberto Pagani , Bruno Murari
发明人： Alberto Pagani , Bruno Murari
IPC分类号： G01N27/00 , G01M5/00 , G01L1/26
CPC分类号： G01N27/00 , G01L1/26 , G01M5/0083
摘要： An electronic device is for detecting and monitoring a local parameter within a solid structure. The electronic device may include an integrated detection module having a functional IC including an integrated sensor to detect the local parameter within the solid structure, and an antenna and having a functional circuitry surface facing towards an outside of the functional IC, and a passivation layer to cover at least the functional circuitry surface of the functional IC so that the functional IC is hermetically sealed and galvanically insulated from a surrounding environment. The electronic device may also include an RF circuit to be coupled with the integrated detection module and having a remote antenna configured to transmit/receive signals for telecommunications and energy exchange with the antenna. The antenna, the RF circuit, and the remote antenna may wirelessly communicate via an electromagnetic coupling.
摘要翻译：电子设备用于检测和监视固体结构内的局部参数。电子设备可以包括具有功能IC的集成检测模块，该功能IC包括用于检测固体结构内的局部参数的集成传感器，以及具有面向功能IC外部的功能电路表面的天线，以及钝化层至少覆盖功能IC的功能电路表面，使得功能IC与周围环境气密密封和电隔离。电子设备还可以包括要与集成检测模块耦合的RF电路，并且具有被配置为发送/接收用于与天线的电信和能量交换的信号的远程天线。天线，RF电路和远程天线可以通过电磁耦合进行无线通信。

35. 发明授权

US09008785B2 Retinal prosthesis 有权
标题翻译：视网膜假体
公开(公告)号：US09008785B2
公开(公告)日：2015-04-14
申请号：US13977121
申请日：2011-12-30
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： A61F2/14 , A61F9/08 , A61N1/05 , A61N1/36
CPC分类号： A61F2/14 , A61F2/148 , A61F9/08 , A61F2250/0002 , A61N1/0543 , A61N1/36 , A61N1/36046
摘要： A retinal prosthesis including an electronic stimulation unit housed inside an eye and including: a plurality of electrodes that contact a portion of a retina of the eye; an electronic control circuit, which is electrically connected to the electrodes and supplies to the electrodes electrical stimulation signals designed to stimulate the portion of retina; and a local antenna connected to the electronic control circuit. The retinal prosthesis further includes an electromagnetic expansion housed inside the eye and formed by a first expansion antenna and a second expansion antenna electrically connected together, the first expansion antenna being magnetically or electromagnetically coupled to an external antenna, the second expansion antenna being magnetically or electromagnetically couple to the local antenna, the electromagnetic expansion moreover receiving an electromagnetic supply signal transmitted by the external antenna and generating a corresponding replica signal.
摘要翻译：一种视网膜假体，包括容纳在眼睛内的电子刺激单元，包括：多个电极，其接触眼睛的视网膜的一部分; 电子控制电路，电连接到电极并向电极提供设计成刺激视网膜部分的电刺激信号; 以及连接到电子控制电路的本地天线。视网膜假体还包括容纳在眼睛内部并由第一扩展天线和电连接在一起的第二扩展天线形成的电磁膨胀，第一扩展天线被磁或电磁耦合到外部天线，第二扩展天线是磁性或电磁学的耦合到本地天线，电磁膨胀还接收由外部天线发送的电磁供给信号并产生相应的复制信号。

36. 发明授权

US08941401B2 Test circuit of an integrated circuit on a wafer 有权
标题翻译：晶圆上集成电路的测试电路
公开(公告)号：US08941401B2
公开(公告)日：2015-01-27
申请号：US13093738
申请日：2011-04-25
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/303 , G01R31/307 , G01R31/317 , G01R31/28 , G01R31/26 , G01R31/302 , G01R31/3185 , G01R35/00
CPC分类号： G01R31/31716 , G01R31/2884 , G01R31/3025 , G01R31/318511 , G01R35/00
摘要： A test circuit is described of a circuit integrated on wafer of the type comprising at least one antenna of the embedded type comprising at least one test antenna associated with said at least one embedded antenna that realizes its connection of the wireless loopback type creating a wireless channel for said at least one embedded antenna and allows its electric test, transforming an electromagnetic signal of communication between said at least one embedded antenna and said at least one test antenna into an electric signal that can be read by a test apparatus.
摘要翻译：描述了集成在晶片上的电路的测试电路，该电路包括至少一个嵌入式天线，包括与所述至少一个嵌入式天线相关联的至少一个测试天线，其实现其无线环回类型的连接，从而创建无线信道对于所述至少一个嵌入式天线并允许其电测试，将所述至少一个嵌入式天线与所述至少一个测试天线之间的通信的电磁信号变换成可由测试设备读取的电信号。

37. 发明申请

US20130342186A1 INTEGRATED ELECTRONIC DEVICE FOR MONITORING PARAMETERS WITHIN A SOLID STRUCTURE AND MONITORING SYSTEM USING SUCH A DEVICE 有权
标题翻译：用于在固体结构中监测参数的集成电子设备和使用这种设备的监视系统
公开(公告)号：US20130342186A1
公开(公告)日：2013-12-26
申请号：US13996259
申请日：2011-10-20
申请人： Alberto Pagani , Bruno Murari
发明人： Alberto Pagani , Bruno Murari
IPC分类号： G01N27/00
CPC分类号： G01N27/00 , G01L1/26 , G01M5/0083
摘要： Device (100) for detecting and monitoring local parameters within a solid structure (300). The device comprises an integrated detection module (1) made on a single chip, having an integrated functional circuitry portion (16) comprising at least one integrated sensor (10) and an integrated antenna (11), and electromagnetic means (2) for transmitting/receiving signals and energy exchange. The integrated functional circuitry portion (16) comprises a functional surface (18) facing towards the outside of the chip. A passivation layer (15) is arranged to completely cover at least the functional surface (18), so that the integrated detection module (1) is entirely hermetically sealed and galvanically insulated from the surrounding environment. The integrated antenna (11), the electromagnetic means (2) and the remote antenna (221) are operatively connected wirelessly through magnetic or electromagnetic coupling.
摘要翻译：用于检测和监测固体结构（300）内的局部参数的装置（100）。该装置包括在单个芯片上制成的集成检测模块（1），其具有包括至少一个集成传感器（10）和集成天线（11）的集成功能电路部分（16），以及电磁装置（2） /接收信号和能量交换。集成功能电路部分（16）包括面向芯片外部的功能表面（18）。钝化层（15）布置成完全覆盖至少功能表面（18），使得集成检测模块（1）完全被气密密封并与周围环境电隔离。集成天线（11），电磁装置（2）和远程天线（221）通过磁或电磁耦合无线地可操作地连接。

38. 发明授权

US08604816B2 Probe card for testing integrated circuits 有权
标题翻译：用于测试集成电路的探针卡
公开(公告)号：US08604816B2
公开(公告)日：2013-12-10
申请号：US12809964
申请日：2008-12-19
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/00 , G01R31/20
CPC分类号： G01R31/2889 , B62M25/04 , G01R1/0491 , G01R1/06727 , G01R1/07342
摘要： An embodiment of a probe card adapted for testing at least one integrated circuit integrated on a corresponding at least one die of a semiconductor material wafer, the probe card including a board adapted for the coupling to a tester apparatus, and a plurality of probes coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units, each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test, the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.
摘要翻译：适于测试集成在半导体材料晶片的相应的至少一个管芯上的至少一个集成电路的探针卡的实施例，所述探针卡包括适于耦合到测试仪器的板，以及耦合到所述板，其中所述探针卡包括多个可更换的基本单元，每个所述基座单元包括用于接触被测集成电路的外部可接近端子的所述探针中的至少一个，所述多个可更换基本单元被布置为对应于涉及包含待测试的集成电路的半导体材料晶片上的至少一个管芯的布置。

39. 发明申请

US20110109342A1 CROSSTALK SUPPRESSION IN WIRELESS TESTING OF SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件无线测试中的CROSSTALK抑制
公开(公告)号：US20110109342A1
公开(公告)日：2011-05-12
申请号：US13006942
申请日：2011-01-14
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/02
CPC分类号： G01R31/2851 , G01R31/2886 , G01R31/3025 , G01R31/303 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.
摘要翻译：一种集成在半导体材料裸片上并适于至少部分地被无线测试的集成电路，其中用于设置用于集成电路的无线测试的所选无线电通信频率的电路集成在半导体材料裸片上。

40. 发明申请

US20100308855A1 PROBE CARD FOR TESTING INTEGRATED CIRCUITS 有权
标题翻译：用于测试集成电路的探针卡
公开(公告)号：US20100308855A1
公开(公告)日：2010-12-09
申请号：US12809964
申请日：2008-12-19
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/00
CPC分类号： G01R31/2889 , B62M25/04 , G01R1/0491 , G01R1/06727 , G01R1/07342
摘要： An embodiment of a probe card adapted for testing at least one integrated circuit integrated on a corresponding at least one die of a semiconductor material wafer, the probe card including a board adapted for the coupling to a tester apparatus, and a plurality of probes coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units, each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test, the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.
摘要翻译：适于测试集成在半导体材料晶片的相应的至少一个管芯上的至少一个集成电路的探针卡的实施例，所述探针卡包括适于耦合到测试仪器的板，以及耦合到所述板，其中所述探针卡包括多个可更换的基本单元，每个所述基座单元包括用于接触被测集成电路的外部可接近端子的所述探针中的至少一个，所述多个可更换基本单元被布置为对应于涉及包含待测试的集成电路的半导体材料晶片上的至少一个管芯的布置。

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