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31. 发明授权

US07747927B2 Method for adapting a memory system to operate with a legacy host originally designed to operate with a different memory system 有权
标题翻译：用于使存储器系统适应原始设计用于与不同存储器系统一起操作的旧式主机进行操作的方法
公开(公告)号：US07747927B2
公开(公告)日：2010-06-29
申请号：US11285992
申请日：2005-11-22
申请人： Daniel C. Guterman , Yoram Cedar , Charles Schroter , Milton Lourenco Barrocas , Carlos Gonzalez , Kevin M. Conley
发明人： Daniel C. Guterman , Yoram Cedar , Charles Schroter , Milton Lourenco Barrocas , Carlos Gonzalez , Kevin M. Conley
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F13/1694 , G06F11/1068 , G11C7/00
摘要： A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.
摘要翻译：非易失性存储器件具有控制器，并且包括控制存储器操作并模拟传统存储器件的存储器和通信特性的方法。以这种方式，存储器设备与最初设计用于操作传统存储设备的主机兼容。特别地，控制器考虑到诸如多位存储器，错误校正要求，覆盖的存储器支持以及可擦除块大小之类的差异，对主机执行仿真。

32. 发明授权

US07669004B2 Flash storage system with write-erase abort detection mechanism 有权
标题翻译：闪存存储系统具有写擦除中止检测机制
公开(公告)号：US07669004B2
公开(公告)日：2010-02-23
申请号：US11936440
申请日：2007-11-07
申请人： Jason T. Lin , Kevin M. Conley , Robert C. Chang
发明人： Jason T. Lin , Kevin M. Conley , Robert C. Chang
IPC分类号： G06F12/00
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/105 , G11C2216/16
摘要： The present invention presents a non-volatile memory and method for its operation that ensures reliable mechanism for write and erase abort detection in the event of lost of power during non-volatile memory programming and erasing with minimized system performance penalty. During a multi-sector write process, an indication of a successful write in one sector is written into the overhead of the following sector at the same time as the following sector's data content is written. The last sector written will additionally have an indication of its own successful write written into its overhead. For erase, an erase abort flag in the first sector of the block can be marked after a successful erase operation.
摘要翻译：本发明提供了一种用于其操作的非易失性存储器和方法，其确保在非易失性存储器编程和擦除期间由于在最小化的系统性能损失下的擦除而导致的写入和擦除中止检测的可靠机制。在多扇区写入过程中，在写入下一个扇区的数据内容的同时，在一个扇区中成功写入的指示被写入下一个扇区的开销。写入的最后一个部分将另外显示自己的成功写入写入其开销。为了擦除，可以在成功擦除操作之后标记块的第一个扇区中的擦除中止标志。

33. 发明授权

US07523013B2 Methods of end of life calculation for non-volatile memories 有权
标题翻译：非易失性存储器寿命计算方法
公开(公告)号：US07523013B2
公开(公告)日：2009-04-21
申请号：US11383384
申请日：2006-05-15
申请人： Sergey Anatolievich Gorobets , Kevin M. Conley
发明人： Sergey Anatolievich Gorobets , Kevin M. Conley
IPC分类号： G06F3/01
CPC分类号： G06F11/008 , G11C16/349 , G11C16/3495
摘要： A system and methods are given for providing information on the amount of life remaining for a memory having a limited lifespan, such as a flash memory card. For example, it can provide a user with the amount of the memory's expected remaining lifetime in real time units (i.e., hours or days) or as a percentage of estimated initial life. An end of life warning can also be provided. In a particular embodiment, the amount of remaining life (either as a percentage or in real time units) can be based on the average number of erases per block, but augmented by the number of spare blocks or other parameters, so that an end of life warning is given if either the expected amount of remaining life falls below a certain level or the number of spare blocks falls below a safe level.
摘要翻译：给出了提供关于具有有限寿命的存储器（例如闪存卡）的剩余寿命的信息的系统和方法。例如，它可以向用户提供实时单位（即，小时或天）中的存储器的预期剩余寿命的量，或作为估计的初始寿命的百分比。也可以提供生命警告的结束。在特定实施例中，剩余寿命的量（以百分比或实时单位计）可以基于每个块的平均擦除次数，但是增加了备用块的数量或其他参数，使得结束如果预期的剩余生命量低于一定水平或备用块数量低于安全水平，则会发出生命警告。

34. 发明申请

US20080307508A1 Method for using time from a trusted host device 有权
标题翻译：从可信主机设备使用时间的方法
公开(公告)号：US20080307508A1
公开(公告)日：2008-12-11
申请号：US11811346
申请日：2007-06-08
申请人： Kevin M. Conley , Michael Holtzman , Rotem Sela , Ron Barzilai , Fabrice E. Jogand-Coulomb
发明人： Kevin M. Conley , Michael Holtzman , Rotem Sela , Ron Barzilai , Fabrice E. Jogand-Coulomb
IPC分类号： G06F21/00
CPC分类号： G06F21/10 , G06F21/725 , G11B20/00086 , Y10S705/901 , Y10S705/912
摘要： A method for using time from a trusted host device is disclosed. In one embodiment, an application on a memory device receives a request to perform a time-based operation from an entity authenticated by the memory device, wherein the entity is running on a host device. The application selects time from the host device instead of time from a time module on the memory device to perform the time-based operation and uses the time from the host device to perform the time-based operation. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.
摘要翻译：公开了一种从可信主机设备使用时间的方法。在一个实施例中，存储设备上的应用从由存储器设备认证的实体接收执行基于时间的操作的请求，其中所述实体在主机设备上运行。应用程序从主机设备中选择时间，而不是从存储设备上的时间模块开始执行时间操作，并使用主机设备执行时间操作的时间。公开了其它实施例，并且每个实施例可以单独使用或组合使用。

35. 发明授权

US07447066B2 Memory with retargetable memory cell redundancy 有权
标题翻译：具有可重定向内存单元冗余的内存
公开(公告)号：US07447066B2
公开(公告)日：2008-11-04
申请号：US11270410
申请日：2005-11-08
申请人： Kevin M. Conley , Yoram Cedar
发明人： Kevin M. Conley , Yoram Cedar
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C29/81 , G11C16/0483 , G11C16/16 , G11C29/808 , G11C29/82
摘要： In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.
摘要翻译：在具有冗余列的存储器阵列中，一种方案允许故障单元被单独地重新映射到冗余列中的冗余单元。一个冗余列中的冗余单元格可以替换多个非冗余列中的有缺陷单元。重新映射作为初始测试和配置的一部分完成。具体硬件可用于方案或固件在内存控制器中可实现的方案。

36. 发明申请

US20080166898A1 METHOD OF MAKING AN EXPANDABLE AND COLLAPSIBLE PERIPHERAL DEVICE 审中-公开
标题翻译：制造可扩展和可折叠外围设备的方法
公开(公告)号：US20080166898A1
公开(公告)日：2008-07-10
申请号：US11620530
申请日：2007-01-05
申请人： Jonathan Hubert , Jason P. Hanlon , Kevin M. Conley
发明人： Jonathan Hubert , Jason P. Hanlon , Kevin M. Conley
IPC分类号： H05K1/14
CPC分类号： G06K19/077
摘要： An expandable and collapsible peripheral device is disclosed, along with methods of manufacturing same. When in an expanded state, the peripheral device may have a length which conforms to the ExpressCard standard, and when in a collapsed state, the peripheral device may have a form factor approximating that of a CompactFlash card. Peripheral devices of the present invention may operate according to standards other than the ExpressCard standard, and may have sizes in the expanded and collapsed positions unrelated to ExpressCards and/or CompactFlash cards.
摘要翻译：公开了可扩展和可折叠的外围设备及其制造方法。当处于扩展状态时，外围设备可以具有符合ExpressCard标准的长度，并且当处于折叠状态时，外围设备可以具有接近CompactFlash卡的形状因子。本发明的外围设备可以根据ExpressCard标准以外的标准进行操作，并且可以具有与ExpressCard和/或CompactFlash卡无关的扩展位置和折叠位置的尺寸。

37. 发明授权

US07301807B2 Writable tracking cells 有权
标题翻译：可追踪单元格
公开(公告)号：US07301807B2
公开(公告)日：2007-11-27
申请号：US11064529
申请日：2005-02-22
申请人： Shahzad B. Khalid , Daniel C. Guterman , Geoffrey S. Gongwer , Richard Simko , Kevin M. Conley
发明人： Shahzad B. Khalid , Daniel C. Guterman , Geoffrey S. Gongwer , Richard Simko , Kevin M. Conley
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C7/14 , G11C7/06 , G11C11/5642 , G11C27/005 , G11C2211/5634
摘要： The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.
摘要翻译：本发明提出了使用可写跟踪单元的几种技术。为存储器的每个写入块提供多个跟踪单元。每当相关联的写入块的用户单元被优选地同时使用相同的固定的全局参考电平来写入时，这些单元被重新编程，以设置跟踪和用户单元编程的阈值。每次读取用户单元时，读取跟踪单元的阈值电压，并且这些阈值用于确定用户单元的存储的逻辑电平。在一组实施例中，一个或多个跟踪单元的群体与多状态存储器的不同逻辑电平相关联。这些跟踪单元群可以仅提供逻辑电平的子集。基于该子集，针对所有逻辑电平导出用于转换阈值电压的读取点。在一个实施例中，由多个跟踪单元组成的两个群组与多位单元的两个逻辑电平相关联。在模拟实现中，使用跟踪单元格群体的模拟阈值直接读取用户单元，而不首先将其转换为数字值。一组替代实施例提供使用不同的电压和/或定时来跟踪单元的写入，以便在跟踪单元的最终写入阈值中提供较小的不确定性。

38. 发明授权

US07184306B2 Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks 有权
标题翻译：闪存EEPROM系统具有同时多个数据扇区编程和存储其他指定块中的物理块特性
公开(公告)号：US07184306B2
公开(公告)日：2007-02-27
申请号：US11323576
申请日：2005-12-29
申请人： Kevin M. Conley , John S. Mangan , Jeffrey G. Craig
发明人： Kevin M. Conley , John S. Mangan , Jeffrey G. Craig
IPC分类号： G11C16/04
CPC分类号： G11C16/107 , G06F12/0246 , G06F2212/7203 , G06F2212/7207 , G06F2212/7208 , G11C16/10 , G11C16/3459 , G11C29/82 , G11C2216/14
摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.
摘要翻译：非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。该系统包括可以单独地或以各种协作组合实现的多个特征。一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围，使得容易制造具有不同容量的存储器芯片的存储器系统。存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

40. 发明授权

US06538922B1 Writable tracking cells 有权
标题翻译：可追踪单元格
公开(公告)号：US06538922B1
公开(公告)日：2003-03-25
申请号：US09671793
申请日：2000-09-27
申请人： Shahzad B. Khalid , Daniel C. Guterman , Geoffrey S. Gongwer , Richard Simko , Kevin M. Conley
发明人： Shahzad B. Khalid , Daniel C. Guterman , Geoffrey S. Gongwer , Richard Simko , Kevin M. Conley
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C7/06 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C27/005 , G11C2211/5621 , G11C2211/5634
摘要： The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.
摘要翻译：本发明提出了使用可写跟踪单元的几种技术。为存储器的每个写入块提供多个跟踪单元。每当相关联的写入块的用户单元被优选地同时使用相同的固定的全局参考电平来写入时，这些单元被重新编程，以设置跟踪和用户单元编程的阈值。每次读取用户单元时，读取跟踪单元的阈值电压，并且这些阈值用于确定用户单元的存储的逻辑电平。在一组实施例中，一个或多个跟踪单元的群体与多状态存储器的不同逻辑电平相关联。这些跟踪单元群可以仅提供逻辑电平的子集。基于该子集，针对所有逻辑电平导出用于转换阈值电压的读取点。在一个实施例中，由多个跟踪单元组成的两个群组与多位单元的两个逻辑电平相关联。在模拟实现中，使用跟踪单元格群体的模拟阈值直接读取用户单元，而不首先将其转换为数字值。一组替代实施例提供使用不同的电压和/或定时来跟踪单元的写入，以便在跟踪单元的最终写入阈值中提供较小的不确定性。

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