专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06305462B1 Door mechanism of automobile air conditioner 有权
标题翻译：汽车空调门机构
公开(公告)号：US06305462B1
公开(公告)日：2001-10-23
申请号：US09297271
申请日：1999-04-28
申请人： Akihiro Tsurushima , Toshiyuki Yoshida , Masaharu Onda , Toshiya Uchida , Katsuaki Koshida , Katsuhiro Kurokawa
发明人： Akihiro Tsurushima , Toshiyuki Yoshida , Masaharu Onda , Toshiya Uchida , Katsuaki Koshida , Katsuhiro Kurokawa
IPC分类号： F25B2900
CPC分类号： B60H1/0005 , B60H1/00692 , B60H1/00857 , Y10T137/87812
摘要： A mix door (5) is arranged in air passages (10, 11) of an automotive air conditioning device. The mix door (5) is arranged to extend in a direction to shut an air flow blown from the upstream air passage (10) and swelled in a downstream direction with a predetermined radius of curvature. The door (5) is guided by arcuate cam grooves (19) and driven upward and downward to achieve open/close operation with the aid of a sliding mechanism (M). Compact construction, reduction in air flow resistance, smoothed handling, high sealing and high temperature controlling are achieved.
摘要翻译：混合门（5）布置在汽车空调装置的空气通道（10,11）中。混合门（5）布置成沿着关闭从上游空气通道（10）吹出的空气流并以预定的曲率半径在下游方向膨胀的方向延伸。门（5）由弓形凸轮槽（19）引导并且被上下驱动，以借助于滑动机构（M）来实现打开/关闭操作。实现紧凑的结构，降低气流阻力，平滑处理，高密封和高温控制。

32. 发明授权

US6137348A Semiconductor device for generating two or more different internal voltages 失效
标题翻译：用于产生两个或多个不同内部电压的半导体器件
公开(公告)号：US6137348A
公开(公告)日：2000-10-24
申请号：US204171
申请日：1998-12-03
申请人： Toshiya Uchida , Yoshimasa Yagishita
发明人： Toshiya Uchida , Yoshimasa Yagishita
IPC分类号： G11C11/413 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/407 , G11C29/06 , G05F1/10
CPC分类号： G05F1/465
摘要： A novel semiconductor device having two different power circuits is disclosed. Even if the output of the stage before a voltage conversion circuit declines due to the decline of the level of the power circuits or the voltage drop through a resistor, the voltage conversion circuit performs a normal operation. The semiconductor device comprises a first power circuit for generating a first source voltage, a second power circuit for generating a second source voltage higher than the first source voltage, and a second power level detection circuit for detecting the second source voltage. The first power circuit changes the first source voltage in accordance with the result of detection by the second power level detection circuit.
摘要翻译：公开了一种具有两个不同功率电路的新型半导体器件。即使由于电源电路的电平下降或通过电阻器的电压降而在电压转换电路之前的级的输出下降，所以电压转换电路执行正常操作。半导体器件包括用于产生第一源电压的第一电源电路，用于产生高于第一源电压的第二源电压的第二电源电路，以及用于检测第二源电压的第二功率电平检测电路。第一电源电路根据第二功率电平检测电路的检测结果改变第一电源电压。

33. 发明授权

US5953247A Dram with dummy word lines 有权
标题翻译：戏剧与虚拟字线
公开(公告)号：US5953247A
公开(公告)日：1999-09-14
申请号：US222175
申请日：1998-12-29
申请人： Hideyuki Kojima , Toshiya Uchida
发明人： Hideyuki Kojima , Toshiya Uchida
IPC分类号： H01L27/10 , G11C8/14 , G11C11/4099 , H01L21/8242 , H01L27/108 , G11C11/24
CPC分类号： H01L27/10897 , G11C11/4099 , G11C8/14 , H01L27/10891
摘要： A plurality of word lines are disposed on the surface of a semiconductor substrate in a first direction. Two dummy word lines are disposed outside of the outermost word line among the word lines. MISFETs are disposed in correspondence with the word lines and dummy word lines. MISFETs are regularly disposed in the first direction and in a second direction crossing the first direction. One storage region among the source and drain regions of each MISFET is formed with a storage contact hole. The storage regions are distributed only in an area inside of the outermost dummy word line among the dummy word lines. A capacitor is connected to the storage region at the bottom of each storage contact hole. Different voltages are applied to the dummy word lines and the bit regions disposed outside of the outermost dummy word line. A semiconductor device capable of suppressing a standby current error is provided.
摘要翻译：多个字线在第一方向上设置在半导体衬底的表面上。两条虚拟字线被设置在字线之间的最外侧字线之外。 MISFET与字线和虚拟字线对应设置。 MISFET通常沿第一方向和与第一方向交叉的第二方向设置。每个MISFET的源区和漏区中的一个存储区形成有存储接触孔。存储区域仅分布在虚拟字线中的最外侧虚拟字线的内侧的区域。电容器连接到每个存储接触孔的底部的存储区域。不同的电压被施加到伪字线和位于最外面的伪字线之外的位区域。提供能够抑制待机电流误差的半导体器件。

34. 发明授权

US5930183A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5930183A
公开(公告)日：1999-07-27
申请号：US978374
申请日：1997-11-25
申请人： Kazumi Kojima , Toshiya Uchida
发明人： Kazumi Kojima , Toshiya Uchida
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C7/00 , G11C8/00 , G11C16/04
CPC分类号： G11C29/789 , G11C29/70 , G11C29/808
摘要： According to the present invention, there is provided a semiconductor memory device comprising a memory cell array and a redundant memory cell array in which a defective cell in the memory cell array is substituted by a cell in the redundant memory cell array; further comprising: a PROM circuit in which a redundant address corresponding to the defective cell is recorded; a redundant address data holding circuit that holds the data of the redundant address recorded in the PROM circuit on initialisation; a circuit for deciding on redundancy that compares the data held by the redundant address data holding circuit with an address supplied from outside and makes a decision; and a driver circuit for the memory cell array that is actuated in accordance with the result of this decision by the circuit for deciding on redundancy and a driver circuit for the redundant memory cell array. Since a semiconductor memory device as above does not have a PROM circuit that delays the operation in the circuit for deciding on redundancy, high-speed operation of the circuit for deciding on redundancy can be achieved. As a result, overall access time can be reduced.
摘要翻译：根据本发明，提供了一种半导体存储器件，包括存储单元阵列和冗余存储单元阵列，其中存储单元阵列中的缺陷单元被冗余存储单元阵列中的单元代替; 进一步包括：PROM电路，其中记录与所述有缺陷单元相对应的冗余地址; 冗余地址数据保持电路，其在初始化时保存记录在PROM电路中的冗余地址的数据; 用于确定将冗余地址数据保持电路保存的数据与从外部提供的地址进行比较的冗余判定电路，以及根据该决定的结果来激活用于确定冗余的电路的存储单元阵列的驱动器电路和用于冗余存储单元阵列的驱动器电路。由于如上所述的半导体存储器件不具有延迟用于决定冗余的电路中的操作的PROM电路，因此可以实现用于决定冗余的电路的高速操作。结果，总体访问时间可以减少。

35. 发明授权

US5694361A Output circuit 失效
标题翻译：输出电路
公开(公告)号：US5694361A
公开(公告)日：1997-12-02
申请号：US376089
申请日：1995-01-20
申请人： Toshiya Uchida
发明人： Toshiya Uchida
IPC分类号： G11C7/10 , H03K19/00 , H03K19/017 , G11C7/00
CPC分类号： G11C7/106 , G11C7/1051 , H03K19/0016 , H03K19/01707
摘要： The turn-on time of an output transistor is minimized to suppress the average value of the load current, and the load is electrically charged with an intermediate potential prior to outputting data to suppress the instantaneous value of the load current. The output circuit holds the load in an open state when a predetermined reset signal has a first logic level, and drives the load from a high-potential side power source or a low-potential side power source depending on the logic level of the output data when said predetermined reset signal changes to a second logic level, wherein the timing at which the reset signal changes from the first logic to the second logic is delayed at least until the logic level of the output data has settled. Furthermore, the load is driven at an intermediate potential between the high-potential side power source voltage, and the low-potential side power source voltage and is then driven on the high-potential side power source or the low-potential side power source depending on the logic level of the output data.
摘要翻译：输出晶体管的导通时间被最小化以抑制负载电流的平均值，并且在输出数据之前负载以中间电位充电以抑制负载电流的瞬时值。当预定的复位信号具有第一逻辑电平时，输出电路将负载保持在打开状态，并根据输出数据的逻辑电平从高电位侧电源或低电位侧电源驱动负载当所述预定复位信号变为第二逻辑电平时，其中复位信号从第一逻辑变为第二逻辑的定时至少延迟至输出数据的逻辑电平已经稳定。此外，负载被驱动在高电位侧电源电压和低电位侧电源电压之间的中间电位，然后在高电位侧电源或低电位侧电源上驱动依赖在输出数据的逻辑电平上。

36. 发明授权

US5579272A Semiconductor memory device with data compression test function and its testing method 失效
标题翻译：具有数据压缩测试功能的半导体存储器件及其测试方法
公开(公告)号：US5579272A
公开(公告)日：1996-11-26
申请号：US563797
申请日：1995-11-28
申请人： Toshiya Uchida
发明人： Toshiya Uchida
IPC分类号： G06F12/16 , G11C11/401 , G11C29/26 , G11C29/34 , G11C29/40 , G11C7/00 , G11C29/00
CPC分类号： G11C29/40 , G11C29/26
摘要： The inputs of matching detection circuits 4i (i=0 to 3) is connected with each of one-bit data lines to one of a plurality of memory blocks 10 to 13, with its output connected to data terminal 2i. The input of distribution circuit 3i are connected to the data terminal 2i and its plurality of outputs, which are insulated from one another and output data corresponding to the data provided to the inputs are connected to the data lines that are connected to the inputs of the matching detection circuit 4i. A control circuit 16 that, during a data write in data compression test mode, invalidates the output from the matching detection circuit 4i to the data terminal 2i and validates outputs from the distribution circuit 3i to the data lines, and during a data read in the the data compression test mode, validates the output from the matching detection circuits 4i to the data terminal 2i and invalidates the outputs from the distribution circuits 3i to the data lines.
摘要翻译：匹配检测电路4i（i = 0〜3）的输入端与1比特数据线中的每一个连接到多个存储器块10至13中的一个，其输出连接到数据终端2i。分配电路3i的输入连接到数据端子2i，并且其多个彼此绝缘的输出和与提供给输入的数据相对应的输出数据连接到连接到输入的数据线匹配检测电路4i。控制电路16，在数据压缩测试模式下的数据写入期间，将匹配检测电路4i的输出无效化到数据端子2i，并验证从分配电路3i到数据线的输出，并且在数据读取期间数据压缩测试模式验证从匹配检测电路4i到数据终端2i的输出，并使从分配电路3i到数据线的输出无效。

37. 发明申请

US20100146201A1 MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM 有权
公开(公告)号：US20100146201A1
公开(公告)日：2010-06-10
申请号：US12612215
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

38. 发明授权

US07483331B2 Semiconductor memory, memory system, and operation method of memory system 有权
标题翻译：半导体存储器，存储器系统和存储器系统的操作方法
公开(公告)号：US07483331B2
公开(公告)日：2009-01-27
申请号：US11455673
申请日：2006-06-20
申请人： Toshiya Uchida
发明人： Toshiya Uchida
IPC分类号： G11C8/00
CPC分类号： G11C11/406 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C8/12 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/408 , G11C11/4096
摘要： A memory system includes a semiconductor memory having a plurality of banks; and a controller accessing the semiconductor memory. The number of the banks is larger than the number of banks simultaneously accessed. When receiving an access command for the bank currently executing the access operation, the semiconductor memory activates a busy signal and keeps the busy signal active until the access operation currently executed is completed. The controller stops outputting a next access command while receiving the activated busy signal. Based on the received busy signal, the controller judges whether or not the next access command should be outputted to the semiconductor memory. Consequently, it is possible to easily execute the random access in a semiconductor memory having a plurality of banks, without giving any load to the system side, which can improve the data transfer rate at the time of the random access.
摘要翻译：存储器系统包括具有多个存储体的半导体存储器; 以及访问半导体存储器的控制器。银行数量大于同时访问的银行数量。当接收当前执行访问操作的银行的访问命令时，半导体存储器激活忙信号并使忙信号有效直到当前执行的访问操作完成。控制器在接收到激活的忙信号的同时停止输出下一个访问命令。根据收到的忙信号，控制器判断是否应该向半导体存储器输出下一个访问命令。因此，可以容易地在具有多个存储体的半导体存储器中执行随机存取，而不会给系统侧带来任何负担，这可以提高随机存取时的数据传输速率。

39. 发明申请

US20080181027A1 Memory device, memory controller and memory system 有权
公开(公告)号：US20080181027A1
公开(公告)日：2008-07-31
申请号：US12000952
申请日：2007-12-19
申请人： Takahiro Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiro Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

40. 发明授权

US07323789B2 Multiple chip package and IC chips 有权
标题翻译：多芯片封装和IC芯片
公开(公告)号：US07323789B2
公开(公告)日：2008-01-29
申请号：US11043993
申请日：2005-01-28
申请人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
发明人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/49113 , H01L2924/3011 , H01L2924/00
摘要： A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.
摘要翻译：时钟输出板和返回时钟接收焊盘设置在集成电路芯片的靠近侧面的部分和与集成电路芯片的与侧面相反的另一侧的部分的逻辑芯片上。时钟接收垫分别在靠近侧面和另一侧的部分设置在存储器芯片上。时钟接收板电连接到时钟输出板和返回时钟接收板。多个时钟信号从逻辑芯片提供给存储器芯片，并且多个返回时钟信号从存储器芯片返回到逻辑芯片。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式