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31. 发明授权

US07704895B2 Deposition method for high-k dielectric materials 失效
标题翻译：高k电介质材料沉积方法
公开(公告)号：US07704895B2
公开(公告)日：2010-04-27
申请号：US12061584
申请日：2008-04-02
申请人： Adrien R. Lavoie , John J. Plombon , Juan E. Dominguez , Harsono S. Simka , Mansour Moinpour
发明人： Adrien R. Lavoie , John J. Plombon , Juan E. Dominguez , Harsono S. Simka , Mansour Moinpour
IPC分类号： H01L21/473
CPC分类号： H01L21/316 , C23C18/1216 , C23C18/1225 , C23C18/1245
摘要： A method for depositing a high-k dielectric material on a semiconductor substrate is disclosed. The method includes applying a chemical bath to a surface of a substrate, rinsing the surface, applying a co-reactant bath to the surface of the substrate, and rinsing the surface. The chemical bath includes a metal precursor which includes at least a hafnium compound, an aluminium compound, a titanium compound, zirconium compound, a scandium compound, a yttrium compound or a lanthanide compound.
摘要翻译：公开了一种在半导体衬底上沉积高k电介质材料的方法。该方法包括将化学浴施加到基底表面上，冲洗表面，向基底表面施加共反应物浴，并漂洗该表面。化学浴包括至少包含铪化合物，铝化合物，钛化合物，锆化合物，钪化合物，钇化合物或镧系元素化合物的金属前体。

32. 发明申请

US20100098960A1 MAGNETIC INSULATOR NANOLAMINATE DEVICE FOR INTEGRATED SILICON VOLTAGE REGULATORS 审中-公开
标题翻译：用于集成硅电压调节器的磁选绝缘体纳米酸盐器件
公开(公告)号：US20100098960A1
公开(公告)日：2010-04-22
申请号：US11764539
申请日：2007-06-18
申请人： Juan E. Dominguez , Arnel M. Fajardo , Adrien R. Lavoie
发明人： Juan E. Dominguez , Arnel M. Fajardo , Adrien R. Lavoie
IPC分类号： B32B15/04 , B05D5/12
CPC分类号： H01L23/645 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/14 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/3011 , H01L2924/00
摘要： A magnetic insulator nanolaminate device comprises a metal magnetic layer formed on a substrate, an insulating layer formed on the metal magnetic layer, wherein the insulating layer is formed by nitriding a portion of the metal magnetic layer, a chelating group layer formed on the insulating layer, and a metal seed layer bonded to the chelating group layer. The magnetic insulator nanolaminate device may be formed by depositing a metal layer on a substrate, converting a portion of the metal layer into an insulating layer using a nitridation process, and depositing a metal seed layer onto the insulating layer using a metal immobilization process, wherein the metal seed layer enables the deposition of a metal layer onto the insulating layer.
摘要翻译：一种磁性绝缘体纳米材料装置，其特征在于，在基板上形成有金属磁性层，形成在所述金属磁性层上的绝缘层，所述绝缘层通过对所述金属磁性层的一部分进行氮化而形成，所述绝缘层形成在所述绝缘层上和与螯合基团层结合的金属种子层。可以通过在基板上沉积金属层，使用氮化工艺将金属层的一部分转换为绝缘层，并使用金属固定工艺将金属种子层沉积到绝缘层上来形成磁性绝缘体纳米材料器件，其中金属种子层能够将金属层沉积到绝缘层上。

33. 发明申请

US20090022958A1 AMORPHOUS METAL-METALLOID ALLOY BARRIER LAYER FOR IC DEVICES 审中-公开
标题翻译：用于IC器件的非晶金属 - 金属合金障碍层
公开(公告)号：US20090022958A1
公开(公告)日：2009-01-22
申请号：US11779894
申请日：2007-07-19
申请人： John J. Plombon , Harsono S. Simka , Adrien R. Lavoie , Juan E. Dominguez
发明人： John J. Plombon , Harsono S. Simka , Adrien R. Lavoie , Juan E. Dominguez
IPC分类号： H01L21/768 , B32B3/10
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/76828 , Y10T428/24545
摘要： A method for fabricating an amorphous metal-metalloid alloy layer for use in an IC device comprises providing a substrate in a reactor that includes a dielectric layer having a trench, pulsing a metal precursor into the reactor to deposit within the trench, wherein the metal precursor is selected from the group consisting of CpTa(CO)4, PDMAT, TBTDET, TaCl5, Cp2Co, Co-amidinates, Cp2Ru, Ru-diketonates, and Ru(CO)4, purging the reactor after the metal precursor pulse, pulsing a metalloid precursor into the reactor to react with the metal precursor and form an amorphous metal-metalloid alloy layer, wherein the metalloid precursor is selected from the group consisting of BH3, BCl3, catechol borane, AlMe3, methylpyrrolidinealane, AICl3, SiH4, SiH2Cl2, SiCl4, tetraalkylsilanes, GeH4, GeH2Cl2, GeCl4, SnCl4, trialkylantimony, SbMe3, SbEt3, arsine, and trimethylarsine, purging the reactor after the metalloid precursor pulse, and annealing the amorphous metal-metalloid layer at a temperature between 50° C. and 700° C. for 5 to 1200 seconds.
摘要翻译：一种用于制造用于IC器件的非晶金属 - 准金属合金层的方法包括在反应器中提供衬底，该反应器包括具有沟槽的电介质层，将金属前体脉冲入反应器以沉积在沟槽内，其中金属前体选自CpTa（CO）4，PDMAT，TBTDET，TaCl5，Cp2Co，Co-脒基物，Cp2Ru，Ru-二酮酸酯和Ru（CO）4），在金属前体脉冲之后进行反应，脉冲准金属前体进入反应器以与金属前体反应并形成无定形金属 - 准金属合金层，其中准金属前体选自BH3，BCl3，儿茶酚硼烷，AlMe3，甲基吡咯烷烃，AICl3，SiH4，SiH2Cl2，SiCl4，四烷基硅烷，GeH 4，GeH 2 Cl 2，GeCl 4，SnCl 4，三烷基锑，SbMe 3，SbEt 3，胂和三甲基胂，在准金属前体脉冲之后吹扫反应器，并在温度下降退火无定形金属 - 在50°C和700°C下烘烤5至1200秒。

34. 发明授权

US07476615B2 Deposition process for iodine-doped ruthenium barrier layers 有权
标题翻译：碘掺杂钌屏障层的沉积工艺
公开(公告)号：US07476615B2
公开(公告)日：2009-01-13
申请号：US11591792
申请日：2006-11-01
申请人： Joseph H. Han , Harsono S. Simka , Adrien R. Lavoie , Juan E. Dominguez , John J. Plombon
发明人： Joseph H. Han , Harsono S. Simka , Adrien R. Lavoie , Juan E. Dominguez , John J. Plombon
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , C23C16/18 , C23C16/45529 , C23C18/08 , C23C18/1216 , C23C18/1295 , C23C18/1605 , C23C18/165 , C23C18/1889 , C25D5/02 , C25D7/123 , H01L21/28556 , H01L21/28562 , H01L21/76846 , H01L21/76873
摘要： An iodine-doped ruthenium barrier layer for use with copper interconnects within integrated circuits is formed using novel, iodine-containing ruthenium precursors in an ALD or CVD process. Ruthenium precursors that may be used include ruthenium containing carbonyls, arenes, cyclopentadienyls, and certain other ruthenium containing compounds. The ruthenium precursors include iodine to catalyze a subsequent copper metal deposition and to smooth the surface of the ruthenium layer. The iodine concentration across the thickness of the ruthenium barrier layer may be constant or may be graded.
摘要翻译：在ALD或CVD工艺中使用新颖的含碘钌前体形成在集成电路内与铜互连一起使用的掺碘钌阻挡层。可以使用的钌前体包括含钌的羰基，芳烃，环戊二烯基和某些其它含钌化合物。钌前体包括碘以催化随后的铜金属沉积并平滑钌层的表面。钌阻挡层的厚度上的碘浓度可以是恒定的或可以分级的。

35. 发明申请

US20080237861A1 Novel Fluorine-Free Precursors and Methods for the Deposition of Conformal Conductive Films for Nanointerconnect Seed and Fill 有权
标题翻译：新型无氟前体和沉淀Nanointerconnect种子和填料的保形导电膜的方法
公开(公告)号：US20080237861A1
公开(公告)日：2008-10-02
申请号：US11694677
申请日：2007-03-30
申请人： Juan E. Dominguez , Adrien R. Lavoie , John J. Plombon , Joseph H. Han , Harsono S. Simka , Bryan C. Hendrix , Gregory T. Stauf
发明人： Juan E. Dominguez , Adrien R. Lavoie , John J. Plombon , Joseph H. Han , Harsono S. Simka , Bryan C. Hendrix , Gregory T. Stauf
IPC分类号： H01L23/52 , H01L21/3205
CPC分类号： H01L21/76843 , C23C16/18 , H01L21/28556 , H01L21/28562 , H01L21/32051 , H01L21/32056 , H01L21/76861 , H01L21/76873
摘要： A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor.
摘要翻译：一种包括在基材存在下引入无氟有机金属前体的方法; 以及根据原子层或化学气相沉积工艺在所述衬底上形成包括所述有机金属前体的部分的导电层。一种包括通过电介质层形成开口到接触点的方法; 引入无氟铜膜前体和共反应物; 并在开口中形成含铜种子层。一种包括计算机的系统，所述计算机包括电耦合到印刷电路板的微处理器，所述微处理器包括由无氟有机金属前体形成的导电互连结构。

36. 发明申请

US20080223287A1 Plasma enhanced ALD process for copper alloy seed layers 审中-公开
标题翻译：铜合金种子层的等离子体增强ALD工艺
公开(公告)号：US20080223287A1
公开(公告)日：2008-09-18
申请号：US11724361
申请日：2007-03-15
申请人： Adrien R. Lavoie , Juan E. Dominguez
发明人： Adrien R. Lavoie , Juan E. Dominguez
IPC分类号： C30B23/00
CPC分类号： C23C16/18 , C23C16/045 , C23C16/45529 , C23C16/45542 , H01L21/28562 , H01L21/76873
摘要： A method of forming a copper alloy seed layer comprises providing a substrate in a reactor, performing a first ALD process to fabricate an alloy metal layer on the substrate, wherein the first ALD process uses an alloy metal precursor selected from a group of specific alloy metal precursors, performing a second ALD process to fabricate a copper metal layer on the alloy metal layer, wherein the second ALD process uses a copper metal precursor selected from a group of specific copper metal precursors, and annealing the alloy metal layer and the copper metal layer to form a graded Cu-alloy layer.
摘要翻译：一种形成铜合金种子层的方法包括在反应器中提供基底，执行第一ALD工艺以在基底上制造合金金属层，其中第一ALD工艺使用选自特定合金金属的合金金属前体前体，执行第二ALD工艺以在合金金属层上制造铜金属层，其中第二ALD工艺使用选自特定铜金属前体的铜金属前体，并退火合金金属层和铜金属层以形成渐变的Cu合金层。

37. 发明申请

US20080064205A1 Silicon-alloy based barrier layers for integrated circuit metal interconnects 失效
标题翻译：用于集成电路金属互连的硅基合金阻挡层
公开(公告)号：US20080064205A1
公开(公告)日：2008-03-13
申请号：US11517736
申请日：2006-09-07
申请人： Juan E. Dominguez , Adrien R. Lavoie
发明人： Juan E. Dominguez , Adrien R. Lavoie
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , C23C16/34 , C23C16/342 , C23C16/45523 , H01L21/28556 , H01L21/28562 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a silicon alloy based barrier layer comprises providing a substrate having a dielectric layer including a trench, placing the substrate in a reactor, and carrying out a process cycle, wherein the process cycle comprises introducing a silicon containing precursor into the reactor, introducing a metal containing precursor into the reactor, and introducing a co-reactant into the reactor, wherein the silicon, metal, and co-reactant react to form a silicon alloy layer that is conformally deposited on a bottom and a sidewall of the trench.
摘要翻译：一种用于形成基于硅合金的阻挡层的方法包括提供具有包括沟槽的介电层的衬底，将衬底放置在反应器中并执行工艺循环，其中工艺循环包括将含硅前体引入反应器中，将含金属的前体引入反应器中，并将共反应物引入反应器中，其中硅，金属和共反应物反应以形成共形沉积在沟槽的底部和侧壁上的硅合金层。

38. 发明授权

US07435679B2 Alloyed underlayer for microelectronic interconnects 有权
标题翻译：用于微电子互连的合金底层
公开(公告)号：US07435679B2
公开(公告)日：2008-10-14
申请号：US11006844
申请日：2004-12-07
申请人： Steven W. Johnston , Juan E. Dominguez
发明人： Steven W. Johnston , Juan E. Dominguez
IPC分类号： H01L21/44
CPC分类号： H01L21/76808 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76858 , H01L23/5226 , H01L23/53238 , H01L28/65 , H01L2924/0002 , H01L2924/00
摘要： Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.
摘要翻译：制造具有作为阻挡层和种子层两者的底层的微电子互连的装置和方法。底层是通过共沉积贵金属和诸如难熔金属的阻挡材料形成的，或者在热后处理之后形成，例如热退火，在两个分开沉积贵金属和阻挡材料之后进行彼此基本溶解。在底层内使用阻挡材料防止互连导电材料的电迁移，并且在底层内使用贵金属允许互连导电材料的直接电镀。

39. 发明授权

US07459392B2 Noble metal barrier and seed layer for semiconductors 有权
标题翻译：贵金属屏障和半导体种子层
公开(公告)号：US07459392B2
公开(公告)日：2008-12-02
申请号：US11096345
申请日：2005-03-31
申请人： Steven W. Johnston , Juan E. Dominguez , Michael L. McSwiney
发明人： Steven W. Johnston , Juan E. Dominguez , Michael L. McSwiney
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L21/76871
摘要： A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region between the barrier and noble metal layers to prevent oxidation of the barrier layer.
摘要翻译：描述了用于半导体镶嵌工艺的阻挡层和籽晶层。种子层由贵金属形成，在阻挡层和贵金属层之间具有中间区域，以防止阻挡层氧化。

40. 发明授权

US07687225B2 Optical coatings 失效
标题翻译：光学涂料
公开(公告)号：US07687225B2
公开(公告)日：2010-03-30
申请号：US10955601
申请日：2004-09-29
申请人： Sergei V. Koveshnikov , Juan E. Dominguez , Kyle Y. Flanigan , Ernisse Putna
发明人： Sergei V. Koveshnikov , Juan E. Dominguez , Kyle Y. Flanigan , Ernisse Putna
IPC分类号： G03F1/00 , B44C1/22
CPC分类号： G03F7/091 , Y10S438/95 , Y10S438/964
摘要： Systems and techniques involving optical coatings for semiconductor devices. An implementation includes a substantially isotropic, heterogeneous anti-reflective coating having a substantially equal thickness normal to any portion of a substrate independent of the orientation of the portion.
摘要翻译：涉及半导体器件光学涂层的系统和技术。实施方案包括基本上各向同性的多相抗反射涂层，其具有与基底的取向无关的垂直于基底的任何部分的基本相等的厚度。

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