专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06828230B2 Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same 失效
标题翻译：具有由相同层结构形成的不同高度的导电路径的集成电路及其形成方法
公开(公告)号：US06828230B2
公开(公告)日：2004-12-07
申请号：US09388824
申请日：1999-09-01
申请人： Aaron Schoenfeld , Rajesh Somasekharan
发明人： Aaron Schoenfeld , Rajesh Somasekharan
IPC分类号： H01L2128
CPC分类号： H01L27/10885 , H01L21/76838 , H01L23/5283 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a substrate having a surface. A first conductive path is disposed on the substrate at a first level and has a first height. A second conductive path is also disposed on the substrate at the first level and has a second height that is significantly different than the first height. Where the integrated circuit is a memory circuit, the digit lines formed from a layer can have a smaller height than other signal lines that are formed from the same layer. Thus, the capacitive coupling between the digit lines can be reduced without degrading the current carrying capability of the other signal lines.
摘要翻译：集成电路包括具有表面的基板。第一导电路径设置在基底上的第一水平并具有第一高度。第二导电路径也被设置在第一层的衬底上，并具有与第一高度显着不同的第二高度。在集成电路是存储电路的地方，由层形成的数字线可以具有比由相同层形成的其它信号线更小的高度。因此，可以减少数字线之间的电容耦合，而不降低其他信号线的电流承载能力。

32. 发明授权

US06707096B2 Fork-like memory structure for ULSI DRAM and method of fabrication 失效
标题翻译：用于ULSI DRAM的叉状存储器结构及其制造方法
公开(公告)号：US06707096B2
公开(公告)日：2004-03-16
申请号：US10038635
申请日：2002-01-03
申请人： Aaron Schoenfeld , Manny Kin F. Ma
发明人： Aaron Schoenfeld , Manny Kin F. Ma
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10817 , Y10S438/947
摘要： A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.
摘要翻译：在形成存储单元电容器期间的掩蔽和蚀刻技术，其同时将存储多晶分离成单个存储多晶节点并将凹槽蚀刻到存储多晶节点中，这增加了存储多晶硅节点的表面积，从而增加了完成的存储器的电容电池没有额外的处理步骤。

33. 发明授权

US06699734B2 Method and apparatus for coupling a semiconductor die to die terminals 有权
标题翻译：用于将半导体管芯耦合到管芯端子的方法和装置
公开(公告)号：US06699734B2
公开(公告)日：2004-03-02
申请号：US10355790
申请日：2003-01-31
申请人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
发明人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
IPC分类号： H01K7144
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49838 , H01L23/642 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/49433 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012
摘要： A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals. The first and second conductive members may each have an intermediate portion between the first and second end portions thereof that is narrower than the second end portions thereof, and the conductive members may be staggered by axially offsetting the second end portion of the second conductive member from the second end portion of the first conductive member.
摘要翻译：一种用于将半导体管芯耦合到其中容纳管芯的管芯封装的端子的方法和装置。该装置包括具有第一和第二端子的模具。第一导电构件在第一端部和第二端部之间延长，使得第二端部接近第一端子。第二导电构件在第一端部部分和第二端部部分之间延伸，使得第二导电构件的第二端部部分靠近模具的第二端子，并且第二导电构件大致平行于第一导电构件。第一和第二导电构件的第二端部分别可以与导电耦合器耦合到第一和第二模具端子。导电构件和导电耦合器的尺寸和形状可以在模具端子处产生选定的电容和/或选定的阻抗。第一和第二导电构件可以在其第一和第二端部之间各自具有比其第二端部窄的中间部分，并且导电构件可以通过使第二导电构件的第二端部轴向偏移而交错第一导电部件的第二端部。

34. 发明授权

US06576987B2 Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die 有权
公开(公告)号：US06576987B2
公开(公告)日：2003-06-10
申请号：US09888885
申请日：2001-06-25
申请人： Aaron Schoenfeld , Jerry M. Brooks
发明人： Aaron Schoenfeld , Jerry M. Brooks
IPC分类号： H01L2941
CPC分类号： H01L23/49541 , H01L23/4951 , H01L23/49568 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/07802 , H01L2924/10253 , H01L2924/14 , Y10T29/49121 , Y10T29/49169 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.

35. 发明授权

US06396727B1 Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same 有权
标题翻译：具有由相同层结构形成的不同高度的导电路径的集成电路及其形成方法
公开(公告)号：US06396727B1
公开(公告)日：2002-05-28
申请号：US09505943
申请日：2000-02-15
申请人： Aaron Schoenfeld , Rajesh Somasekharan
发明人： Aaron Schoenfeld , Rajesh Somasekharan
IPC分类号： G11C502
CPC分类号： H01L27/10885 , H01L21/76838 , H01L23/5283 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a substrate having a surface. A first conductive path is disposed on the substrate at a first level and has a first height. A second conductive path is also disposed on the substrate at the first level and has a second height that is significantly different than the first height. Where the integrated circuit is a memory circuit, the digit lines formed from a layer can have a smaller height than other signal lines that are formed from the same layer. Thus, the capacitive coupling between the digit lines can be reduced without degrading the current carrying capability of the other signal lines.
摘要翻译：集成电路包括具有表面的基板。第一导电路径设置在基底上的第一水平并具有第一高度。第二导电路径也被设置在第一层的衬底上，并具有与第一高度显着不同的第二高度。在集成电路是存储电路的地方，由层形成的数字线可以具有比由相同层形成的其它信号线更小的高度。因此，可以减少数字线之间的电容耦合，而不降低其他信号线的电流承载能力。

36. 发明授权

US06348400B1 Method and apparatus for implementing selected functionality on an integrated circuit device 失效
标题翻译：用于在集成电路设备上实现所选功能的方法和装置
公开(公告)号：US06348400B1
公开(公告)日：2002-02-19
申请号：US09441238
申请日：1999-11-16
申请人： Aaron Schoenfeld
发明人： Aaron Schoenfeld
IPC分类号： H01L2144
CPC分类号： H01L24/06 , H01L23/52 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/4826 , H01L2224/484 , H01L2224/48464 , H01L2224/48599 , H01L2224/48699 , H01L2224/4903 , H01L2224/49051 , H01L2224/49113 , H01L2224/49171 , H01L2224/4941 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01023 , H01L2924/01047 , H01L2924/01079 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , Y10S257/923 , H01L2924/00
摘要： A semiconductor device is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon connected to the integrated circuitry. At least one electrically conductive wire bond is made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads, which are not interconnected via the integrated circuitry within the die. The first bond pad can be a lead finger on the active surface and the second bond pad can be an option bond pad electrically connected to a third bond pad selected from the plurality of bond pads on the active surface via the integrated circuitry. Further, the third bond pad can connect to a fourth bond pad selected from the plurality of bond pads via a wire bond. The first bond pad can also be an internal voltage line and the second bond pad an external voltage line or the bond pads can be different internal buses within the integrated circuitry.
摘要翻译：公开了一种半导体器件，其包括具有有源表面轴承集成电路的管芯，管芯包括连接到集成电路的多个接合焊盘。在多个接合焊盘的第一和第二接合焊盘之间形成至少一个导电引线接合，用于在两个接合焊盘之间提供外部电连接，这两个接合焊盘之间不通过管芯内的集成电路互连。第一接合焊盘可以是有源表面上的引线指，并且第二接合焊盘可以是通过集成电路电连接到从有源表面上的多个接合焊盘中选择的第三接合焊盘的选项接合焊盘。此外，第三接合焊盘可以经由引线键连接到从多个接合焊盘中选择的第四接合焊盘。第一接合焊盘也可以是内部电压线，并且第二接合焊盘外部电压线或接合焊盘可以是集成电路内的不同内部总线。

37. 发明授权

US06316976B1 Method and apparatus for improving the performance of digital delay locked loop circuits 有权
标题翻译：用于提高数字延迟锁定环路电路性能的方法和装置
公开(公告)号：US06316976B1
公开(公告)日：2001-11-13
申请号：US09560848
申请日：2000-04-28
申请人： James E. Miller, Jr. , Aaron Schoenfeld , Manny Ma , R. Jacob Baker
发明人： James E. Miller, Jr. , Aaron Schoenfeld , Manny Ma , R. Jacob Baker
IPC分类号： H03L706
CPC分类号： H03L7/10 , H03K5/133 , H03L7/0814
摘要： A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.
摘要翻译：一种用于通过使用唯一的校正锁存器和新颖的复位机制电路来提高数字延迟锁定环（DDLL）的性能和精度的方法和装置，用于消除DDLL最小和最大延迟状态的不可操作性。通过使用三非门逻辑延迟元件设计，DDLL的精度进一步提高。根据本发明的DDLL在每个延迟线元件的输出处提供信号的对称上升沿和下降沿。根据本发明的DDLL进一步确保初始化时对随机值的不敏感性。此外，根据本发明的DDLL由于确保在相位检测操作期间实际的而不是分频的输入信号与输出信号之间的比较而提高了精度。

38. 发明授权

US6066515A Multilevel leadframe for a packaged integrated circuit 失效
公开(公告)号：US6066515A
公开(公告)日：2000-05-23
申请号：US72889
申请日：1998-05-05
申请人： Aaron Schoenfeld
发明人： Aaron Schoenfeld
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L24/48 , H01L23/4951 , H01L24/49 , H01L2224/05554 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/49112 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/85207 , H01L24/45 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/30107
摘要： The present invention is directed to a packaged semiconductor chip that utilizes a multilevel leadframe that positions the lead fingers close to the bond pads while positioning the bus bars on a different level and behind or outboard of the lead finger connections such that it is unnecessary for any wires to cross over the bus bars or the lead fingers. The leadframe may comprise a multi-part frame, or be fabricated from a single sheet of metal.

39. 发明授权

US6052289A Interdigitated leads-over-chip lead frame for supporting an integrated circuit die 有权
标题翻译：用于支持集成电路管芯的交叉引线芯片引线框架
公开(公告)号：US6052289A
公开(公告)日：2000-04-18
申请号：US141005
申请日：1998-08-26
申请人： Aaron Schoenfeld , Jerry M. Brooks
发明人： Aaron Schoenfeld , Jerry M. Brooks
IPC分类号： H01L23/495 , H05K7/02
CPC分类号： H01L24/06 , H01L23/4951 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/85399 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/07802 , H01L2924/10253 , H01L2924/14
摘要： An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.
摘要翻译：本发明的超导芯片（LOC）引线框架包括构造成覆盖在集成电路（IC）裸片的前侧表面上的双面胶带的交叉引线的组件。每个引线的附接表面可粘合地附接到带上，并且至少一些引线被构造成延伸穿过模具的前侧表面从一个边缘基本上延伸到另一个边缘，例如相邻或相对的边缘。结果，模具的前侧表面的大部分区域通过带子可粘附到引线上，因此模具可以以改进的方式支撑在IC封装中，并且可以将热量从模具通过引线框架以改进的方式。

40. 发明授权

US6010932A Fork-like memory structure for ULSI DRAM and method of fabrication 失效
公开(公告)号：US6010932A
公开(公告)日：2000-01-04
申请号：US759464
申请日：1996-12-05
申请人： Aaron Schoenfeld , Manny Kin F. Ma
发明人： Aaron Schoenfeld , Manny Kin F. Ma
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , Y10S438/947
摘要： A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式