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31. 发明授权

KR100971532B1 구동 트랜지스터를 포함하는 반도체 소자 有权
标题翻译：一个驱动晶体管的半导体器件
公开(公告)号：KR100971532B1
公开(公告)日：2010-07-21
申请号：KR1020080049219
申请日：2008-05-27
申请人： 삼성전자주식회사
发明人： 윤종인 , 정순문 , 김한수 , 장재훈 , 조후성 , 박준범 , 정재훈
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/8221 , H01L27/0688 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： 본 발명은 구동 트랜지스터를 포함하는 반도체 소자를 제공한다. 이 소자는 기판 상에 차례로 적층된 절연막 및 반도체막, 및 반도체막 내에 형성되어 반도체 패턴을 정의하는 격리 트렌치를 채우는 소자분리막을 포함한다. 고전압을 제어하는 구동 트랜지스터가 반도체 패턴에 형성되고, 격리 트렌치의 바닥면은 절연막의 상부면의 일부이다.

32. 发明公开

KR1020100018156A 적층형 반도체 소자 및 그 제조 방법 无效
标题翻译：叠层半导体器件及其制造方法
公开(公告)号：KR1020100018156A
公开(公告)日：2010-02-17
申请号：KR1020080076798
申请日：2008-08-06
申请人： 삼성전자주식회사
发明人： 박준범 , 정순문 , 김한수 , 장재훈 , 정재훈 , 윤종인 , 황미소
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0688 , H01L25/0657 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/12 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE: A stacked semiconductor device and a method of manufacturing the same are provided to prevent a unit elements from being heated and deteriorating by connecting the top semiconductor pattern with the surface of a single crystalline. CONSTITUTION: A first interlayer insulating film(104) is formed on a single crystalline semiconductor substrate(100). A first contact plug(106) connected through the first interlayer insulating film to the single crystalline semiconductor substrate is formed. A top semiconductor pattern(114) is formed on the first interlayer insulating film while contacting the upper side of the first contact plug. An upper transistor including an impurity region and a gate structure(118) is formed on the top semiconductor pattern. Cell transistors provided as a cell array are offered on the single-crystal semiconductor substrate. The upper transistor has an operating voltage different from the cell transistor.
摘要翻译：目的：提供叠层半导体器件及其制造方法，以通过将顶部半导体图案与单晶表面连接来防止单元元件被加热和劣化。构成：在单晶半导体衬底（100）上形成第一层间绝缘膜（104）。形成通过第一层间绝缘膜连接到单晶半导体衬底的第一接触插头（106）。顶部半导体图案（114）形成在第一层间绝缘膜上，同时接触第一接触插塞的上侧。在顶部半导体图案上形成包括杂质区域和栅极结构（118）的上部晶体管。作为单元阵列提供的单体晶体管被提供在单晶半导体衬底上。上部晶体管具有与单元晶体管不同的工作电压。

33. 发明公开

KR1020090123242A 구동 트랜지스터를 포함하는 반도체 소자 有权
标题翻译：一个驱动晶体管的半导体器件
公开(公告)号：KR1020090123242A
公开(公告)日：2009-12-02
申请号：KR1020080049219
申请日：2008-05-27
申请人： 삼성전자주식회사
发明人： 윤종인 , 정순문 , 김한수 , 장재훈 , 조후성 , 박준범 , 정재훈
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/8221 , H01L27/0688 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/1211 , H01L21/845
摘要： PURPOSE: A semiconductor device including a driving transistor is provided to reduce a separation distance between a semiconductor pattern and an adjacent semiconductor pattern by arranging the semiconductor pattern in which a driving transistor is formed on an insulation film. CONSTITUTION: An insulation film and a semiconductor film are successively arranged on a substrate. An isolation film(125) is formed inside the semiconductor film, and fills an isolation trench for defining a first semiconductor pattern(105) and a second semiconductor pattern(108). A first driving transistor(132) is formed in the first semiconductor pattern. A second transistor(134) is formed in the second semiconductor pattern. A floor surface of the isolation trench is a part of a top surface of the insulation film. At least one of the first driving transistor and the second driving transistor controls a high voltage higher than a power voltage.
摘要翻译：目的：提供一种包括驱动晶体管的半导体器件，通过在绝缘膜上布置形成有驱动晶体管的半导体图案来减小半导体图案与相邻的半导体图案之间的间隔距离。构成：在基板上依次配置绝缘膜和半导体膜。在半导体膜内形成隔离膜（125），并填充用于限定第一半导体图案（105）和第二半导体图案（108）的隔离沟槽。第一驱动晶体管（132）形成在第一半导体图案中。第二晶体管（134）形成在第二半导体图案中。隔离沟槽的地板表面是绝缘膜的上表面的一部分。第一驱动晶体管和第二驱动晶体管中的至少一个控制高于电源电压的高电压。

34. 发明授权

KR100928021B1 3차원 어레이 구조를 갖는 반도체 장치 有权
标题翻译： 3차원어레이구조를갖는반도체장치
公开(公告)号：KR100928021B1
公开(公告)日：2009-11-24
申请号：KR1020070058411
申请日：2007-06-14
申请人： 삼성전자주식회사
发明人： 조후성 , 정순문 , 나영섭 , 장재훈 , 정재훈 , 박준범
IPC分类号： H01L21/8247 , H01L27/115
摘要： 3차원 구조를 갖는 반도체 장치가 제공된다. 반도체 장치는 셀 어레이 영역과 셀 어레이 영역에 인접한 로우 디코더 영역을 포함한다. 셀 어레이 영역은 제 1 층에 제 1 게이트 라인을 구비하는 제 1 셀 블록과, 상기 제 1 층 상의 제 2 층에 제 2 게이트 라인을 구비하는 제 2 셀 블록으로 구성된다. 로우 디코더 영역은 상기 제 1 게이트 라인을 제어하는 제 1 로우 디코더 및 상기 제 2 게이트 라인을 제어하는 제 2 로우 디코더로 구성된다. 상기 제 1 게이트 라인과 상기 제 1 로우 디코더를 연결하는 제 1 배선, 및 상기 제 2 게이트 라인과 상기 제 2 로우 디코더를 연결하는 제 2 배선이 있다.
셀 어레이 영역, 로우 디코더, 메탈 콘택
摘要翻译：提供具有三维阵列结构的半导体器件以方便地处理多层的字线，并通过位于单元阵列区域两侧的低解码器充分确保金属接触和金属布线的余量。单元阵列区域包括第一单元块和第二单元块。第一单元块包括单元阵列区域的第一层上的第一栅极线。第二单元块包括在单元阵列区域的第一层之上的第二层上的第二栅极线。低解码器区域与单元阵列区域相邻，并且包括第一低解码器（DEC1）和第二低解码器（DEC2）。其中，第一低位解码器控制第一栅极线，第二低位解码器控制第二栅极线。第一布线连接第一栅极线和第一低解码器。第二布线连接第二栅极线和第二低解码器。

35. 发明公开

KR1020090106869A 3차원 메모리 장치 및 그것의 구동 방법 无效
标题翻译：树的常规存储器件及其驱动方法
公开(公告)号：KR1020090106869A
公开(公告)日：2009-10-12
申请号：KR1020080032261
申请日：2008-04-07
申请人： 삼성전자주식회사
发明人： 윤종인 , 장재훈 , 정순문 , 김한수 , 박준범 , 정재훈
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C16/3418 , G11C16/3427 , H01L27/11551
摘要： PURPOSE: A three dimensional memory device and a driving method thereof are provided to reduce program disturbance by applying different well voltages to the wells of each layer in a program operation. CONSTITUTION: A three dimensional memory device(100) has a plurality of layers. One of the layers is selected. Wells(101,102) of the selected layer is biased to the first well voltage. A word line voltage is applied to the selected word line of the selected layer. The wells of the non-selected layers are biased to a second well voltage. The second well voltage is larger than the first well voltage. Each layer of the three dimensional memory device shares the word line.
摘要翻译：目的：提供一种三维存储器件及其驱动方法，以通过在程序操作中向每层的阱施加不同的阱电压来减少编程干扰。构成：三维存储装置（100）具有多个层。选择其中一个图层。所选择的层的阱（101,102）被偏置到第一阱电压。字线电压被施加到所选层的所选字线。未选择的层的阱被偏压到第二阱电压。第二阱电压大于第一阱电压。三维存储设备的每一层共享字线。

36. 发明公开

KR1020040001275A 샐리사이드 형성 공정을 포함하는 반도체 소자의 제조방법 无效
标题翻译：制造半导体器件的方法，包括杀真菌剂形成过程
公开(公告)号：KR1020040001275A
公开(公告)日：2004-01-07
申请号：KR1020020036415
申请日：2002-06-27
申请人： 삼성전자주식회사
发明人： 정재훈 , 정순문 , 임훈 , 박준범
IPC分类号： H01L29/78
摘要： PURPOSE: A method of manufacturing a semiconductor device is provided to obtain enough space for forming a contact with maintaining a designated channel length by a salicide forming process, and to prevent deterioration of transistor characteristics by performing the annealing process before a source/drain formation process. CONSTITUTION: A plurality of gate electrodes(12) are formed on a semiconductor substrate(10) in which a salicide forming region and a non-salicide forming region are defined. After an LDD(Lightly Doped Drain) region is formed, the first spacer(16) is formed at the side wall of the gate electrode(12). A salicide barrier layer(18) is formed over the first spacer and the gate electrode. The second spacer is formed on the side wall of the first spacer(16) by etching the salicide barrier layer(18) exposed by way of a photolithography method. After source/drain regions(14a,22) is formed by an ion implantation process, a salicide(24) is formed on the source/drain regions and/or the gate electrode, which is located in the salicide forming region. The salicide(24) is formed out of silicide by way of a self-aligning method.
摘要翻译：目的：制造半导体器件的方法是为了获得足够的空间来形成接触，并通过自对准硅化物形成工艺保持指定的沟道长度，并且通过在源极/漏极形成过程之前执行退火工艺来防止晶体管特性的劣化。构成：在半导体衬底（10）上形成多个栅电极（12），其中限定了自对准硅化物形成区域和非硅化物形成区域。在形成LDD（轻掺杂漏极）区域之后，第一间隔物（16）形成在栅电极（12）的侧壁处。在第一间隔物和栅电极上形成自对准硅化物阻挡层（18）。通过蚀刻通过光刻法暴露的自对准硅化物阻挡层（18），在第一间隔物（16）的侧壁上形成第二间隔物。在通过离子注入工艺形成源极/漏极区域（14a，22）之后，在位于自对准硅化物形成区域中的源极/漏极区域和/或栅极电极上形成硅化物（24）。硅化物（24）通过自对准方法由硅化物形成。

37. 发明公开

KR1020090093034A 반도체 장치 및 그의 형성방법 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：KR1020090093034A
公开(公告)日：2009-09-02
申请号：KR1020080018334
申请日：2008-02-28
申请人： 삼성전자주식회사
发明人： 박준범 , 정순문 , 김기남
IPC分类号： H01L27/07 , H01L27/115 , H01L29/78
CPC分类号： H01L27/24 , Y10S977/774 , H01L27/2463 , H01L27/2409 , H01L29/517 , H01L29/7832 , H01L45/06 , H01L45/144
摘要： A semiconductor device and method of forming the same are provided to use the step height between the structures and the semiconductor substrate by active elements. The cell peripheral gate region frame is electrically connected with gate connection patterns(136, 139) through connection holes. The semiconductor substrate has the cell array region and the peripheral circuit region. The common node is located on the semiconductor substrate of the cell array region. The common node has resistive memory portions(R1, R2, R3, R4). The first and second active circuit element is electrically connected with the common node. The insulating layer surrounds the common node, and the first and second active circuit elements while being located on the semiconductor substrate.
摘要翻译：提供一种半导体器件及其形成方法，以通过有源元件使用结构和半导体衬底之间的台阶高度。电池外围栅极区域框架通过连接孔与栅极连接图案（136,139）电连接。半导体衬底具有电池阵列区域和外围电路区域。公共节点位于电池阵列区域的半导体衬底上。公共节点具有电阻性存储器部分（R1，R2，R3，R4）。第一和第二有源电路元件与公共节点电连接。绝缘层围绕公共节点以及位于半导体衬底上的第一和第二有源电路元件。

38. 发明公开

KR1020080032586A 비휘발성 메모리 소자 및 그 형성방법 无效
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：KR1020080032586A
公开(公告)日：2008-04-15
申请号：KR1020070024088
申请日：2007-03-12
申请人： 삼성전자주식회사
发明人： 조후성 , 정순문 , 나영섭 , 장재훈 , 정재훈 , 박준범
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/28
CPC分类号： H01L27/2463 , H01L21/28273
摘要： A non-volatile memory device and a method for forming the same are provided to process word lines of multi layer conveniently according to the allocation of a low decoder, and to acquire margin of metal contact and metal wiring sufficiently by the low decoder, so that the non-volatile memory device can be formed into a stacked structure. A cell array region comprises a first cell array and a second cell array provided on the first cell array. A first low decoder(DEC1) is connected with a first word line(WL1) of the first cell array. A second low decoder(DEC2) is connected with a second word line(WL2) of the second cell array. A first metal contact(120) is connected with the first word line. A first metal wiring(140) connects the first metal contact and the first low decoder. A second metal contact(220) is connected with the second word line. A second metal wiring(240) connects the second low decoder with the second metal contact.
摘要翻译：提供了一种非易失性存储器件及其形成方法，以便根据低解码器的分配方便地处理多层的字线，并通过低解码器充分获取金属接触和金属布线的余量，从而非易失性存储器件可以形成为堆叠结构。单元阵列区域包括设置在第一单元阵列上的第一单元阵列和第二单元阵列。第一低解码器（DEC1）与第一单元阵列的第一字线（WL1）连接。第二低解码器（DEC2）与第二单元阵列的第二字线（WL2）连接。第一金属触点（120）与第一字线连接。第一金属布线（140）连接第一金属触点和第一低解码器。第二金属触点（220）与第二字线连接。第二金属布线（240）将第二低解码器与第二金属触点连接。

39. 发明公开

KR1020170129381A 클럭 신호 생성기 및 기판 검사 장치 审中-实审
标题翻译：时钟信号发生器和基片检测装置
公开(公告)号：KR1020170129381A
公开(公告)日：2017-11-27
申请号：KR1020160059990
申请日：2016-05-17
申请人： 삼성전자주식회사
发明人： 박준범 , 강경식 , 김태중 , 석상옥 , 전병환
IPC分类号： G01N21/89 , H05K13/08 , G01N21/88 , G02B21/00 , G01J1/44
CPC分类号： G02B21/365 , G01N21/8806 , G01N21/8851 , G01N21/9501 , G02B21/0096 , G02B26/105
摘要： 클럭신호생성기는입사되는광을제1 방향으로스캐닝하도록회전가능한광학미러, 상기제1 방향과다른제2 방향으로배열되고상기광학미러로부터반사된광이상기제1 방향으로스캐닝될때 상기광을차단하거나통과시키는복수개의격자어레이들을포함하고상기격자어레이는인접한격자어레이에대하여상기제1 방향으로기 설정된거리만큼쉬프트된격자플레이트, 상기격자어레이들을통해통과한광을검출하는광 검출기, 및상기광 검출기로부터수신한검출신호들로부터클럭신호를생성하기위한픽셀클럭생성유닛을포함한다.
摘要翻译：时钟信号发生器块当入射光的在第一方向上排列，所述第二方向，可旋转光学镜，所述第一方向进行扫描与所述光的至少一个基体1由光学反射镜的光或反射的方向扫描的不同其中，光栅阵列包括相对于相邻光栅阵列在第一方向上偏移预定距离的光栅板，用于检测穿过光栅阵列的光的光电检测器以及光检测器以及像素时钟生成单元，用于从接收到的检测信号生成时钟信号。

40. 发明公开

KR1020080027420A 반도체 장치 및 그 형성방법 无效
标题翻译：半导体器件及其形成方法
公开(公告)号：KR1020080027420A
公开(公告)日：2008-03-27
申请号：KR1020060092483
申请日：2006-09-22
申请人： 삼성전자주식회사
发明人： 장영철 , 장재훈 , 정재훈 , 정순문 , 나영섭 , 박준범
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/76 , H01L21/31
CPC分类号： H01L21/28273 , H01L21/02293 , H01L21/31051 , H01L21/76838
摘要： A semiconductor device and a fabricating method thereof are provided to form a semiconductor layer having low resistance by subjecting the semiconductor layer to an ion implantation process. Interlayer dielectrics(180,240) are formed on a semiconductor substrate(100), and a semiconductor layer(200) is formed on the interlayer dielectric. A mold pattern is formed on the semiconductor, and has openings for exposing the semiconductor layer. Semiconductor patterns(210a) are filled in the openings, and are connected to the semiconductor layer. Upper gate lines cross upper portions of the semiconductor patterns. The semiconductor patterns are formed on the semiconductor layer through selective epitaxial growth. The upper gate lines have upper word lines(220).
摘要翻译：提供半导体器件及其制造方法，以通过对半导体层进行离子注入工艺来形成具有低电阻的半导体层。层间电介质（180,240）形成在半导体衬底（100）上，半导体层（200）形成在层间电介质上。在半导体上形成模具图案，并且具有用于使半导体层露出的开口。半导体图案（210a）填充在开口中，并连接到半导体层。上栅极线交叉半导体图案的上部。半导体图案通过选择性外延生长形成在半导体层上。上部栅极线具有上部字线（220）。

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