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    • 33. 发明公开
    • 카스 레이턴시에 따라 1 분주 방식 또는 2 분주 방식의 레이턴시 신호를 발생하는 레이턴시 회로 및 이를 구비하는 반도체 메모리 장치
    • 用于使用一维或二维方法产生信号信号的延迟电路和具有相同功能的半导体存储器件
    • KR1020110023533A
    • 2011-03-08
    • KR1020090081485
    • 2009-08-31
    • 삼성전자주식회사
    • 권상혁정병훈
    • G11C11/4076G11C7/20G11C11/407
    • G11C11/4076G11C7/1084G11C7/222G11C11/4093G11C11/4096G11C2207/2272H03L7/0812
    • PURPOSE: A latency circuit for generating latency signal using 1-division or 2-division method and a semiconductor memory device having the same are provided to improve noise feature of a delay duplication circuit by reducing the number of delay unit in a delay duplication circuit. CONSTITUTION: A latency control clock generator(120) generates a signal having a frequency which is formed by dividing an original frequency by m. A latency control clock generator generates at least one latency control clock. The latency signal generating unit(130) generates a latency signal. The latency control clock generator is comprised of a delay locked loop(121), a clock divider(122), a delay locked loop duplicating unit(123), and an internal read command signal generation duplication unit(124). A delay locked loop generates an in-phase signal. A clock divider divides the in-phase signal by 2 The delay locked loop duplication unit generates an output signal which is synchronized with the external clock. The internal read command signal generation duplication unit generates the latency control clock.
    • 目的:提供一种用于使用1分或2分割方法产生等待时间信号的延迟电路和具有该等待时间信号的半导体存储器件,以通过减少延迟复制电路中的延迟单元的数量来改善延迟复制电路的噪声特征。 构成:延迟控制时钟发生器(120)产生具有通过将原始频率除以m而形成的频率的信号。 延迟控制时钟发生器产生至少一个等待时间控制时钟。 延迟信号生成单元(130)生成等待时间信号。 延迟控制时钟发生器包括延迟锁定环(121),时钟分频器(122),延迟锁定环复制单元(123)和内部读命令信号生成复制单元(124)。 延迟锁定环产生同相信号。 时钟分频器将同相信号除以2延迟锁定环复制单元产生与外部时钟同步的输出信号。 内部读命令信号产生复制单元产生等待时间控制时钟。
    • 34. 发明公开
    • 파워 온 리셋 회로 및 이를 수행하는 방법
    • 上电复位电路及其执行方法
    • KR1020080062233A
    • 2008-07-03
    • KR1020060137749
    • 2006-12-29
    • 삼성전자주식회사
    • 박준석정병훈허낙원
    • H03K17/22
    • H03K17/223H03K3/011
    • A power on reset circuit and a method processing the same are provided to generate upper and lower trip point signals based on a reference value obtained from the amplification of differential amplifier. A power on reset circuit(100) includes a latch initialization unit(110), a trip point signal generation unit(120), and a latch output unit(130). The latch initialization unit generates a first latch initialization signal based on an external voltage that is increased in power on. The trip point signal generation unit generates upper and lower trip point signals based on a reference voltage and the external voltage. The latch output unit generates a second latch initialization signal for initiating a digital IC(Integrated Circuit) based on the first latch initialization signal and the upper and lower trip point signals.
    • 提供上电复位电路及其处理方法,以基于从差分放大器的放大获得的参考值产生上下跳变点信号。 上电复位电路(100)包括锁存初始化单元(110),跳变点信号生成单元(120)和锁存器输出单元(130)。 锁存初始化单元基于在上电时增加的外部电压产生第一锁存初始化信号。 跳变点信号生成单元基于参考电压和外部电压生成上下跳变点信号。 锁存器输出单元产生第二锁存初始化信号,用于基于第一锁存初始化信号和上下跳变点信号启动数字IC(集成电路)。
    • 36. 发明公开
    • 서로 다른 단위 지연 시간을 가지는 지연소자를 구비하는지연 시간 보상 회로
    • 延迟时间补偿电路,包含具有不同单元延迟时间的延迟器件
    • KR1020040050539A
    • 2004-06-16
    • KR1020020078392
    • 2002-12-10
    • 삼성전자주식회사
    • 조근희정병훈김규현
    • H03L7/08
    • H03L7/0814H03K5/135H03K2005/00208H03L7/0818
    • PURPOSE: A delay time compensation circuit comprising delay devices having different unit delay time is provided to reduce the number of delay devices as assuring an operation area of the delay time compensation circuit. CONSTITUTION: According to a delay locked loop making a phase of a feedback clock signal coincide with a phase of an external clock signal, a phase detector compares the phase of the external clock signal with the phase of the feedback clock signal and then outputs their difference as an error control signal. A delay line comprises a plurality of delay devices(410,420,430,440,450,460) having different unit delay time and generates an output clock signal where the phase of the external clock signal is controlled by receiving the external clock signal, and the number of the delay devices is controlled in response to a shift signal. And a filter generates the shift signal selecting the number of the delay devices of the delay line in response to the error control signal.
    • 目的:提供包括具有不同单位延迟时间的延迟装置的延迟时间补偿电路,以便在确定延迟时间补偿电路的操作区域时减少延迟装置的数量。 构成:根据延迟锁定环,使反馈时钟信号的相位与外部时钟信号的相位一致,相位检测器将外部时钟信号的相位与反馈时钟信号的相位进行比较,然后输出它们的差值 作为错误控制信号。 延迟线包括具有不同单位延迟时间的多个延迟器件(410,420,430,440,450,460),并产生输出时钟信号,其中通过接收外部时钟信号来控制外部时钟信号的相位,并且延迟器件的数量被控制在 对移位信号的响应。 并且滤波器响应于误差控制信号产生选择延迟线的延迟装置的数量的移位信号。
    • 37. 发明公开
    • 반도체 장치에 대한 정보를 디지털적으로 읽어내기 위한퓨즈 시그너처 회로
    • 用于读取半导体器件数字信息的保险丝识别电路
    • KR1020040021487A
    • 2004-03-10
    • KR1020020053336
    • 2002-09-04
    • 삼성전자주식회사
    • 정병훈권경환노광숙배원일
    • G11C7/00
    • PURPOSE: A fuse signature circuit for reading digitally information of a semiconductor device is provided to detect correctly the information of the semiconductor device having the signature circuit or the information of package having the semiconductor device by storing digitally the information. CONSTITUTION: A fuse signature circuit for reading digitally information of a semiconductor device includes an enable circuit(221) and one or more switching circuits. The enable circuit(221) is connected between an input pad(211) and a node in order to enable the fuse signature circuit in response to the enable signal. The switching circuits are connected between the node and a ground voltage terminal in order to form a current path between the input pad(211) and the ground voltage terminal in response to corresponding fuses(231-237) and corresponding signals. The switching circuits include transistors(223-229).
    • 目的:提供一种用于读取半导体器件的数字信息的熔丝签名电路,用于通过数字地存储信息来正确地检测具有签名电路的半导体器件的信息或具有半导体器件的封装的信息。 构成:用于读取半导体器件的数字信息的熔丝签名电路包括使能电路(221)和一个或多个开关电路。 使能电路(221)连接在输入焊盘(211)和节点之间,以便响应于使能信号启用熔丝签名电路。 开关电路连接在节点和接地电压端子之间,以响应于相应的保险丝(231-237)和相应的信号在输入焊盘(211)和接地电压端子之间形成电流路径。 开关电路包括晶体管(223-229)。
    • 39. 发明公开
    • 비면허 대역을 사용하는 셀룰러 네트워크에서의 상향링크 자원할당 방법 및 그 장치
    • 用于使用免许可频段在蜂窝网络中分配上行链路资源的方法和装置
    • KR1020170128120A
    • 2017-11-22
    • KR1020170058514
    • 2017-05-11
    • 삼성전자주식회사
    • 박승훈문정민정병훈
    • H04W72/04H04W74/08
    • H04W72/042H04L1/1671H04L1/1861H04W72/0446H04W72/1289H04W74/0808H04W74/0816
    • 본발명은 4G 시스템이후보다높은데이터전송률을지원하기위한 5G 통신시스템을 IoT 기술과융합하는통신기법및 그시스템에관한것이다. 본개시는 5G 통신기술및 IoT 관련기술을기반으로지능형서비스 (예를들어, 스마트홈, 스마트빌딩, 스마트시티, 스마트카 혹은커넥티드카, 헬스케어, 디지털교육, 소매업, 보안및 안전관련서비스등)에적용될수 있다. 본발명의일 실시예에따른기지국의통신방법은, 비면허대역을통해통신가능한적어도두 개의연속된상향링크서브프레임들을포함하는상향링크버스트(burst)에대한정보가포함된자원할당정보를생성하는단계; 자원할당정보를단말에게전송하는단계; 및적어도두 개의연속된상향링크서브프레임들동안단말로부터상향링크데이터를수신하는단계를포함할수 있다.
    • 本发明涉及用于将5G通信系统与IoT技术集成以支持比4G系统更高的数据速率的通信技术和系统。 本实用新型是针对智能服务(例如,基于5G的技术和物联网相关技术,智能家居,智能楼宇,智能城市,智能卡,或连接汽车,医疗,数字教育,零售,保安和安全服务, ),它可以被应用。 根据本发明的一个实施方式的基站的通信方法,用于生成包含关于UL信息的资源分配信息脉冲串(脉冲串),包括至少两个连续的上行链路子帧可以在非授权频带通信 步骤; 传输资源分配信息给终端; 并且从终端接收至少两个连续的上行链路子帧的上行链路数据。