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31. 发明授权

US5941884A Patella preparation apparatus and method 有权
标题翻译：髌骨制备装置及方法
公开(公告)号：US5941884A
公开(公告)日：1999-08-24
申请号：US169030
申请日：1998-10-09
申请人： Amy A. Corvelli , Arthur S. Heissenbuttel , Yu Chang Lin , Bryan J. Smith
发明人： Amy A. Corvelli , Arthur S. Heissenbuttel , Yu Chang Lin , Bryan J. Smith
IPC分类号： A61B17/16 , A61B17/17 , A61B19/00 , A61B17/56
CPC分类号： A61B17/1677 , A61B17/1767 , A61B2017/1602 , A61B2090/034 , A61B2090/061
摘要： A patella clamp and method for use in resecting a patella for the reception of a patellar prosthesis holds the patella in a preparation position and provides the surgeon with a direct and interoperative accurate visual indication of the bone thickness of the patella prior to and subsequent to resection, as well as a direct and interoperative accurate visual indication of an interoperatively settable depth of resection, all without the necessity for introducing supplemental instruments or other apparatus during the resection procedure.
摘要翻译：用于切除髌骨以接受髌骨假体的髌骨夹具和方法将髌骨保持在准备位置，并且在切除之前和之后向外科医生提供对髌骨骨厚度的直接和间接的准确视觉指示，以及直接和互操作的准确的视觉指示手术切除深度，所有这些都不需要在切除手术过程中引入补充仪器或其他设备。

32. 外观设计

USD947996S1 Sensing faucet for integration of soap supply with water exit 有权
公开(公告)号：USD947996S1
公开(公告)日：2022-04-05
申请号：US29732421
申请日：2020-04-24
申请人： Hsiang-Hung Wang , Yu-Chang Lin
设计人： Hsiang-Hung Wang , Yu-Chang Lin

33. 发明申请

US20170218605A1 INFRARED SOAP DISPENSING FAUCET STRUCTURE 审中-公开
公开(公告)号：US20170218605A1
公开(公告)日：2017-08-03
申请号：US15008449
申请日：2016-01-28
申请人： Hsiang-Hung Wang , Yu-Chang Lin
发明人： Hsiang-Hung Wang , Yu-Chang Lin
IPC分类号： E03C1/046 , A47K5/12 , A47K5/14
CPC分类号： E03C1/046 , A47K5/1217 , A47K5/14 , E03C1/0404 , Y02A20/202
摘要： An infrared soap dispensing faucet structure comprises a shell and an automatic soap dispensing unit. The shell has a hollow vertical section with a first space and a hollow horizontal section with a second space. A water outlet and a soap outlet are arranged at an outer lower edge of the horizontal section. The water outlet has a first sensor and the soap outlet has a second sensor. The first sensor of the water outlet is provided for controlling the water outlet to be turned on and off. The shell and the automatic soap dispensing unit are integrated with each other so that a bathroom space is not in disarray and dirt remained on hands is not polluted a faucet or the automatic soap dispensing unit.

34. 发明授权

US09337059B2 Apparatus and methods for annealing wafers 有权
标题翻译：用于退火晶圆的设备和方法
公开(公告)号：US09337059B2
公开(公告)日：2016-05-10
申请号：US13215909
申请日：2011-08-23
申请人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
发明人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC分类号： H01L21/00 , H01L21/324 , H01L21/268 , H01L21/20 , H01L21/36 , H01L21/44
CPC分类号： H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
摘要翻译：一种方法包括在晶片上进行退火。晶片包括晶片边缘区域和由晶片边缘区域包围的内部区域。在退火期间，施加在晶片边缘区域的一部分上的第一功率至少低于用于退火内部区域的第二功率。

35. 发明授权

US08058134B2 Junction profile engineering using staged thermal annealing 有权
标题翻译：接头型材工程采用分段热退火
公开(公告)号：US08058134B2
公开(公告)日：2011-11-15
申请号：US12618052
申请日：2009-11-13
申请人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
发明人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
摘要翻译：退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。第二个持续时间比第一个持续时间长。退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。

36. 发明申请

US20100210086A1 Junction Profile Engineering Using Staged Thermal Annealing 有权
标题翻译：接头型材工程使用分段热退火
公开(公告)号：US20100210086A1
公开(公告)日：2010-08-19
申请号：US12618052
申请日：2009-11-13
申请人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
发明人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
摘要翻译：退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。第二个持续时间比第一个持续时间长。退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。

37. 发明授权

US07736968B2 Reducing poly-depletion through co-implanting carbon and nitrogen 失效
标题翻译：通过共同植入碳和氮来减少多元消耗
公开(公告)号：US07736968B2
公开(公告)日：2010-06-15
申请号：US12259028
申请日：2008-10-27
申请人： Keh-Chiang Ku , Cheng-Lung Hung , Li-Ting Wang , Chien-Hao Chen , Chien-Hao Huang , Wenli Lin , Yu-Chang Lin
发明人： Keh-Chiang Ku , Cheng-Lung Hung , Li-Ting Wang , Chien-Hao Chen , Chien-Hao Huang , Wenli Lin , Yu-Chang Lin
IPC分类号： H01L21/8238
CPC分类号： H01L21/28052 , H01L21/26506 , H01L21/26586 , H01L21/28506 , H01L29/1083 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成栅电极层; 将碳和氮掺杂到栅电极层中; 并且在掺杂碳和氮的步骤之后，分别构图栅极电介质层和栅极电极层以形成栅极电介质和栅电极。

38. 发明授权

US07672101B2 ESD protection circuit and method 有权
标题翻译： ESD保护电路及方法
公开(公告)号：US07672101B2
公开(公告)日：2010-03-02
申请号：US11852799
申请日：2007-09-10
申请人： Shu-Huei Lin , Chong-Gim Gan , Yi-Hsun Wu , Yu-Chang Lin
发明人： Shu-Huei Lin , Chong-Gim Gan , Yi-Hsun Wu , Yu-Chang Lin
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： A system includes a driving device operating at first supply voltage Vdd1 and having a CMOS output. A driven devise operates at a second supply voltage Vdd2 lower than the first supply voltage Vdd1, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor sad a source coupled to a lower-voltage supply rail VSS. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to Vss. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge.
摘要翻译：系统包括以第一电源电压Vdd1操作并具有CMOS输出的驱动装置。驱动装置在低于第一电源电压Vdd1的第二电源电压Vdd2下工作，并具有带NMOS下拉晶体管的CMOS输入。保护电路包括耦合到驱动装置的CMOS输出的第一电阻器和NMOS下拉晶体管的栅极。寄生NPN双极结晶体管具有连接到NMOS下拉晶体管的栅极的漏极和耦合到较低电压电源轨VSS的源极。第二个电阻将寄生NPN双极结晶体管的栅极连接到Vss。第二电阻器的电阻大小用于控制寄生NPN双极结晶体管的触发电压，用于保护NMOS下拉晶体管的栅氧化层免受静电放电。

39. 发明授权

US07342835B2 Memory device with pre-fetch circuit and pre-fetch method 有权
标题翻译：具有预取电路和预取方法的存储器件
公开(公告)号：US07342835B2
公开(公告)日：2008-03-11
申请号：US11105459
申请日：2005-04-14
申请人： Ying Te Tu , Yu Chang Lin
发明人： Ying Te Tu , Yu Chang Lin
IPC分类号： G11C7/10 , G11C11/34 , G11C16/06 , G11C7/00
CPC分类号： G11C11/4076 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C11/406 , G11C11/40607
摘要： A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense amplifiers are coupled to each memory block to at least one of read data from and write data to the selected wordline. A buffer of latches are coupled to the group of first sense amplifiers and have sufficient capacity to hold data corresponding to the selected wordline of memory cells.
摘要翻译：存储器件包括多个存储器块，每个存储器块具有以字线和位线布置的存储单元，以及选择器，用于选择存储器单元的字线。一组第一读出放大器耦合到每个存储器块，以从至所选择的字线的数据读取数据和写入数据中的至少一个。锁存器的缓冲器耦合到第一读出放大器组，并且具有足够的容量来保存对应于存储器单元的选定字线的数据。

40. 发明授权

US06943103B2 Methods for reducing flip chip stress 有权
标题翻译：减少倒装芯片应力的方法
公开(公告)号：US06943103B2
公开(公告)日：2005-09-13
申请号：US10768848
申请日：2004-01-29
申请人： Yia-Liang Kuo , Yu-Chang Lin , Yu-Ting Lin
发明人： Yia-Liang Kuo , Yu-Chang Lin , Yu-Ting Lin
IPC分类号： H01L21/44 , H01L21/60 , H01L23/485
CPC分类号： H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/05001 , H01L2224/05022 , H01L2224/05085 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2224/29099 , H01L2924/00 , H01L2224/05099
摘要： Novel methods for reducing shear stress applied to solder bumps on a flip chip. The methods are particularly applicable to reducing temperature-induced shear stress on solder bumps located adjacent to an empty space on a flip chip during high-temperature testing of the chip. According to a first embodiment, the method includes providing an anchoring solder bump in each empty space on the flip chip. The anchoring solder bumps impart additional structural integrity to the flip chip and prevent shear-induced detachment of solder bumps from the flip chip, particularly those solder bumps located adjacent to each anchoring solder bump. According to a second embodiment, the method includes providing an anchoring solder bump in the empty space and then connecting the anchoring solder bump to an adjacent solder bump on the chip using a solder bridge.
摘要翻译：用于减少施加到倒装芯片上的焊料凸块的剪切应力的新方法。该方法特别适用于在芯片的高温测试期间减少与倒装芯片上的空白空间相邻的焊料凸块上的温度诱导剪切应力。根据第一实施例，该方法包括在倒装芯片上的每个空白空间中提供锚定焊料凸块。锚定焊料凸块对倒装芯片赋予额外的结构完整性，并防止焊料凸块从倒装芯片，特别是位于每个锚定焊料凸块附近的焊料凸块的剪切引起的分离。根据第二实施例，该方法包括在空间中提供锚定焊料凸块，然后使用焊接桥将锚定焊料凸块连接到芯片上的相邻焊料凸块。

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