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    • 32. 发明申请
    • APPARATUS AND METHOD FOR SIMULATING A RECONFIGURABLE PROCESSOR
    • 用于模拟可重构加工器的装置和方法
    • US20110246170A1
    • 2011-10-06
    • US13012945
    • 2011-01-25
    • Tae-Wook OhSoo-Jung RyuYoon-Jin KimWoong SeoYoung-Chul ChoII-Hyun Park
    • Tae-Wook OhSoo-Jung RyuYoon-Jin KimWoong SeoYoung-Chul ChoII-Hyun Park
    • G06F9/45
    • G06F17/5054G06F17/5022G06F17/5077
    • A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.
    • 提供了一种用于评估执行应用程序的处理器性能的处理器模拟技术。 处理器模拟技术可以用于优化应用程序的执行。 包括多个功能单元的可重配置处理器的模拟器包括通过在生成操作数的功能单元和消耗操作数的功能单元之间表示路由路径来建模处理器。 可以根据从调度器接收到的模调度,基于关于功能单元之间的路由延迟和迭代循环的阶段信息的信息来确定每个队列的大小。 还提供了存储用于路由队列操作的面向主机的二进制代码的建模代码DB。 可以通过执行与二进制文件相对应的主机定向二进制代码而不是二进制文件来执行模拟。
    • 40. 发明授权
    • Apparatus and method for simulating a reconfigurable processor
    • 用于模拟可重构处理器的装置和方法
    • US08725486B2
    • 2014-05-13
    • US13012945
    • 2011-01-25
    • Tae-Wook OhSoo-Jung RyuYoon-Jin KimWoong SeoYoung-Chul ChoIl-Hyun Park
    • Tae-Wook OhSoo-Jung RyuYoon-Jin KimWoong SeoYoung-Chul ChoIl-Hyun Park
    • G06F17/50
    • G06F17/5054G06F17/5022G06F17/5077
    • A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.
    • 提供了一种用于评估执行应用程序的处理器性能的处理器模拟技术。 处理器模拟技术可以用于优化应用程序的执行。 包括多个功能单元的可重构处理器的模拟器通过在生成操作数的功能单元之间表示路由路径以及消耗操作数的功能单元来对处理器进行建模。 可以根据从调度器接收到的模调度,基于关于功能单元之间的路由延迟和迭代循环的阶段信息的信息来确定每个队列的大小。 还提供了存储用于路由队列操作的面向主机的二进制代码的建模代码DB。 可以通过执行与二进制文件相对应的主机定向二进制代码而不是二进制文件来执行模拟。