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31. 发明授权

US07074718B2 Method of fabricating a semiconductor device having a buried and enlarged contact hole 有权
标题翻译：制造具有埋入和扩大的接触孔的半导体器件的方法
公开(公告)号：US07074718B2
公开(公告)日：2006-07-11
申请号：US10898485
申请日：2004-07-22
申请人： Seong-Goo Kim , Sang-Moo Jeong
发明人： Seong-Goo Kim , Sang-Moo Jeong
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/331 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76895 , H01L21/76804 , H01L21/76831 , H01L21/76897 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
摘要翻译：根据本发明的实施例，将位线层间绝缘层放置在半导体衬底上。两个相邻位线图案并联放置在位线层间绝缘层上，并且两个相邻位线图案中的每一个都包括位线和位线叠层层图案。掩埋接触层间绝缘层覆盖具有两个相邻位线图案的半导体衬底的表面。接触孔放置在位线图案之间的部分中，以穿透埋入层间绝缘层和位线层间绝缘层，并露出位线图案的至少一个侧壁。接触孔间隔件覆盖接触孔的侧壁。接触孔插头放置在接触孔间隔件上以填充接触孔。

32. 发明申请

US20050017295A1 Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same 有权
标题翻译：具有埋入和扩大的接触孔的半导体器件及其制造方法
公开(公告)号：US20050017295A1
公开(公告)日：2005-01-27
申请号：US10898485
申请日：2004-07-22
申请人： Seong-Goo Kim , Sang-Moo Jeong
发明人： Seong-Goo Kim , Sang-Moo Jeong
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/108 , H01L29/76
CPC分类号： H01L21/76895 , H01L21/76804 , H01L21/76831 , H01L21/76897 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
摘要翻译：根据本发明的实施例，将位线层间绝缘层放置在半导体衬底上。两个相邻位线图案并联放置在位线层间绝缘层上，并且两个相邻位线图案中的每一个都包括位线和位线叠层层图案。掩埋接触层间绝缘层覆盖具有两个相邻位线图案的半导体衬底的表面。接触孔放置在位线图案之间的部分中，以穿透埋入层间绝缘层和位线层间绝缘层，并露出位线图案的至少一个侧壁。接触孔间隔件覆盖接触孔的侧壁。接触孔插头放置在接触孔间隔件上以填充接触孔。

33. 发明授权

US08482045B2 Semiconductor memory device having vertical channel transistor and method for fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及其制造方法
公开(公告)号：US08482045B2
公开(公告)日：2013-07-09
申请号：US13549648
申请日：2012-07-16
申请人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
发明人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
摘要翻译：两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件。像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

34. 发明授权

US08293604B2 Methods of manufacturing vertical channel semiconductor devices 有权
标题翻译：制造垂直沟道半导体器件的方法
公开(公告)号：US08293604B2
公开(公告)日：2012-10-23
申请号：US12838826
申请日：2010-07-19
申请人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11568 , H01L28/91 , H01L29/66833 , H01L29/7926
摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.
摘要翻译：垂直沟道半导体器件包括具有上表面的柱的半导体衬底。绝缘栅电极围绕柱的周边。绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。第一源极/漏极区域在与衬底相邻的衬底中。第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

35. 发明授权

US08174065B2 Semiconductor device having vertical transistor and method of fabricating the same 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US08174065B2
公开(公告)日：2012-05-08
申请号：US12840599
申请日：2010-07-21
申请人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
发明人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
IPC分类号： H01L29/66
CPC分类号： H01L27/10894 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.
摘要翻译：提供了具有垂直晶体管的半导体器件及其制造方法。该方法包括制备具有单元区域和外围电路区域的半导体衬底。在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。位线分离沟槽与垂直栅极结构的列方向平行地形成。位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

36. 发明授权

US07781287B2 Methods of manufacturing vertical channel semiconductor devices 有权
标题翻译：制造垂直沟道半导体器件的方法
公开(公告)号：US07781287B2
公开(公告)日：2010-08-24
申请号：US12022329
申请日：2008-01-30
申请人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11568 , H01L28/91 , H01L29/66833 , H01L29/7926
摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.
摘要翻译：垂直沟道半导体器件包括具有上表面的柱的半导体衬底。绝缘栅电极围绕柱的周边。绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。第一源极/漏极区域在与衬底相邻的衬底中。第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

37. 发明申请

US20080124869A1 METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES 有权
标题翻译：制造垂直通道半导体器件的方法
公开(公告)号：US20080124869A1
公开(公告)日：2008-05-29
申请号：US12022329
申请日：2008-01-30
申请人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11568 , H01L28/91 , H01L29/66833 , H01L29/7926
摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.
摘要翻译：垂直沟道半导体器件包括具有上表面的柱的半导体衬底。绝缘栅电极围绕柱的周边。绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。第一源极/漏极区域在与衬底相邻的衬底中。第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

38. 发明授权

US07348628B2 Vertical channel semiconductor devices and methods of manufacturing the same 有权
标题翻译：垂直沟道半导体器件及其制造方法
公开(公告)号：US07348628B2
公开(公告)日：2008-03-25
申请号：US11448437
申请日：2006-06-07
申请人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/792 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11568 , H01L28/91 , H01L29/66833 , H01L29/7926
摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.
摘要翻译：垂直沟道半导体器件包括具有上表面的柱的半导体衬底。绝缘栅电极围绕柱的周边。绝缘栅电极具有比柱的上表面低的垂直级上的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。第一源极/漏极区域在与衬底相邻的衬底中。第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

39. 发明申请

US20070152255A1 Semiconductor memory device having vertical channel transistor and method for fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及其制造方法
公开(公告)号：US20070152255A1
公开(公告)日：2007-07-05
申请号：US11600568
申请日：2006-11-16
申请人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
发明人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
IPC分类号： H01L29/94
CPC分类号： H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated
摘要翻译：两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件。像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。因此，存储单元的有效空间布置是可能的，使得构成4F 2结构，并且可以应用传统的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

40. 发明申请

US20070087499A1 Semiconductor memory device with vertical channel transistor and method of fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及其制造方法
公开(公告)号：US20070087499A1
公开(公告)日：2007-04-19
申请号：US11546581
申请日：2006-10-11
申请人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
发明人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
IPC分类号： H01L21/8242 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/66666 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/7827
摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.
摘要翻译：在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。形成围绕每个支柱部分的栅电极。位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。第一掺杂区域形成在柱的每个柱部分的上表面中。第二掺杂区形成在柱的主体部分上并与电位线连接。存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

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