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31. 发明授权

US07102905B2 Stacked memory, memory module and memory system 有权
标题翻译：堆叠内存，内存模块和内存系统
公开(公告)号：US07102905B2
公开(公告)日：2006-09-05
申请号：US10979157
申请日：2004-11-03
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： H05K1/181 , G11C5/04 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1005 , H01L2225/1023 , H01L2225/107 , H01L2924/13091 , H01L2924/15311 , H01L2924/15321 , H01L2924/3011 , H05K2201/10159 , H05K2201/10515 , H05K2203/1572 , Y02P70/611 , H01L2924/00014 , H01L2924/00
摘要： A point-to-point bus and a daisy chain bus are provided for supplying signals to stacked memories, and the stacked memories are mounted mutually apart by a distance equivalent to the length of the stacked memory on both surfaces of a module substrate. Furthermore, the memory chips arranged in a stacked memory mounted on one surface are set in an active state at the same time alternately with the memory chips arranged in a stacked memory mounted on another surface of the module substrate.
摘要翻译：提供点对点总线和菊花链总线，用于向堆叠的存储器提供信号，堆叠的存储器相互间隔相隔一定距离，与模块基板的两个表面上堆叠的存储器的长度相当。此外，布置在安装在一个表面上的堆叠存储器中的存储器芯片与安装在模块基板的另一表面上的堆叠存储器中布置的存储芯片交替地设置为活动状态。

32. 发明授权

US07038498B2 Input/output circuit, reference-voltage generating circuit, and semiconductor integrated circuit 有权
公开(公告)号：US07038498B2
公开(公告)日：2006-05-02
申请号：US11000005
申请日：2004-12-01
申请人： Seiji Funaba
发明人： Seiji Funaba
IPC分类号： H03K5/22
CPC分类号： H04L25/028 , H03K19/018592 , H04L25/0278 , H04L25/0292
摘要： Disclosed is an input/output circuit having a terminating circuit that contributes to a smaller chip area. The input/output includes an output buffer having a first series circuit, which comprises a first transistor and a resistor and a second series circuit, which comprises a second transistor and a resistor, connected in parallel between a high-potential power supply and an input/output pin, as well as a third series circuit, which comprises a third transistor and a resistor and a fourth series circuit, which comprises a fourth transistor and a resistor, connected in parallel between the input/output pin and a low-potential power supply. The input/output circuit further includes an input buffer having an input terminal connected to the input/output pin, and a control circuit which, at the time of a signal output, performs control for supplying a signal, which is obtained by inverting the logic of output data, to gates of the first to fourth transistors, and which, at the time of a signal input, performs control for supplying the gates of the first and third transistors with the high-potential power supply voltage and low-potential power supply voltage, respectively, and the gates of the second and fourth transistors with the low-potential power supply voltage and high-potential power supply voltage, respectively.

33. 发明申请

US20060018407A1 Semiconductor device, memory device and memory module having digital interface 失效
公开(公告)号：US20060018407A1
公开(公告)日：2006-01-26
申请号：US10982946
申请日：2004-11-08
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
IPC分类号： H03K9/00
CPC分类号： H03K5/082 , H03K5/135
摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

34. 发明申请

US20050174878A1 Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM 有权
标题翻译：半导体存储器模块，存储器系统，电路，半导体器件和DIMM
公开(公告)号：US20050174878A1
公开(公告)日：2005-08-11
申请号：US11019274
申请日：2004-12-23
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba
IPC分类号： G06F12/00 , G06F1/10 , G06F13/16 , G11C7/10 , G11C7/22 , G11C8/00 , G11C11/4076 , G11C11/4093 , G11C29/02
CPC分类号： G11C29/028 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/50012
摘要： There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.
摘要翻译：存在的问题是，由于DIMM中的C / A信号通过DIMM中的寄存器分配到相应的DRAM，DQ信号直接从DIMM中的端子连接，因此它们的时序难以同步。提供用于加速高速运行的DIMM的C / A信号的寄存器，寄存器的布线设置为菊花链布线。然后，通过设置在DRAM中的定时调整电路，根据DRAM的位置而不同的C / A信号和时钟信号之间的布线延迟时间差使得从寄存器的延迟时间之和并且由于定时调整电路引起的延迟量等于最远的DRAM的延迟时间。

35. 发明授权

US06269051B1 Semiconductor device and timing control circuit 有权
公开(公告)号：US06269051B1
公开(公告)日：2001-07-31
申请号：US09640670
申请日：2000-08-18
申请人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
发明人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.

36. 发明授权

US06212127B1 Semiconductor device and timing control circuit 有权
标题翻译：半导体器件和定时控制电路
公开(公告)号：US06212127B1
公开(公告)日：2001-04-03
申请号：US09563160
申请日：2000-05-01
申请人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
发明人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.
摘要翻译：执行从可变延迟电路的输出到其延迟控制输入的延迟环路的操作速度。例如，分频电路分别置于可变延迟电路的输入和输出端。通过对从可变延迟电路输出的信号进行分频而获得的信号通过虚拟延迟电路被提供给相位比较器的一个输入，并且通过对可变延迟电路的输入进行分频而获得的信号被提供给另一个输入相位比较器。根据两个信号的相位之间的比较结果进行相位控制。

37. 发明申请

US20140232181A1 Automotive Vehicle Inverter Control Apparatus 有权
标题翻译：汽车变频器控制装置
公开(公告)号：US20140232181A1
公开(公告)日：2014-08-21
申请号：US14240811
申请日：2012-07-19
申请人： Masashige Tsuji , Yasuo Noto , Seiji Funaba
发明人： Masashige Tsuji , Yasuo Noto , Seiji Funaba
IPC分类号： H02M7/537 , B60L11/18
CPC分类号： H02M7/537 , B60L11/1803 , B60R16/02 , H02M7/003 , H02M7/42
摘要： In an automotive vehicle inverter control apparatus of the related art, a limp-home mode is provided, but six power sources including transformers are required for respective gate circuits of the respective IGBT drive circuits. Therefore, a reduction in size and a reduction in weight cannot be achieved, and a demand of the improvement of mountability or the improvement of fuel consumption as described above cannot be satisfied. A power semiconductor module and the drive circuit include three unit semiconductor modules and three unit drive circuits corresponding to a three-phase alternating current, and power supply units of the unit drive circuits are provided independently, whereby the limp-home mode is provided and in addition, the number of power supply units may be reduced, so that the reduction in size and the reduction in weight are achieved.
摘要翻译：在现有技术的汽车用逆变器控制装置中，提供了跛脚回位模式，但是对于各个IGBT驱动电路的各个门电路，需要包括六个电源，包括变压器。因此，不能实现小型化和轻量化，不能满足如上所述的安装性的提高或燃料消耗的提高的要求。功率半导体模块和驱动电路包括对应于三相交流电的三个单位半导体模块和三个单元驱动电路，并且独立地提供单元驱动电路的电源单元，从而提供跛脚模式，并且此外，可以减少供电单元的数量，从而实现尺寸的减小和重量的减轻。

38. 发明授权

US08791681B2 Electric power conversion system 有权
标题翻译：电力转换系统
公开(公告)号：US08791681B2
公开(公告)日：2014-07-29
申请号：US13201139
申请日：2010-02-19
申请人： Yoshio Akaishi , Yasuo Noto , Koichi Yahata , Seiji Funaba , Masashige Tsuji
发明人： Yoshio Akaishi , Yasuo Noto , Koichi Yahata , Seiji Funaba , Masashige Tsuji
IPC分类号： H02M3/156
CPC分类号： H02M7/48 , B60L11/1851 , H02M2001/322 , Y02T10/7005 , Y02T10/705
摘要： A power conversion system according to the present invention includes: an inverter circuit unit that converts a direct current power supplied from a direct current source into an alternating current power, the direct current power being supplied to the inverter circuit through a contactor that conducts and interrupts the direct current; a capacitor that smoothes the direct current power; a discharge circuit unit that is connected to the capacitor in parallel, and that includes a discharge resistor for discharging a charge stored in the capacitor and a switching element for the discharge resistor, being connected in series to the discharge resistor; a voltage detection circuit unit that detects voltage between both terminals of the capacitor; a first discharge control circuit that includes a first microcomputer, and that outputs a control signal to control switching of the switching element for discharging; and a second discharge control circuit that outputs an interruption signal to interrupt the switching element for the discharge resistor.
摘要翻译：根据本发明的电力变换系统包括：逆变器电路单元，其将从直流源提供的直流电力转换为交流电力，直流电力通过接触器提供给逆变器电路，所述接触器导通和中断直流电; 一个平滑直流电源的电容器; 放电电路单元，其并联连接到电容器，并且包括用于放电存储在电容器中的电荷的放电电阻器和用于放电电阻器的开关元件串联连接到放电电阻器; 电压检测电路单元，其检测所述电容器的两端之间的电压; 第一放电控制电路，包括第一微型计算机，并且输出控制信号以控制用于放电的开关元件的切换; 以及输出中断信号以中断放电电阻器的开关元件的第二放电控制电路。

39. 发明授权

US08436590B2 Discharge circuit for smoothing capacitor of DC power supply 有权
标题翻译：直流电源滤波电容放电电路
公开(公告)号：US08436590B2
公开(公告)日：2013-05-07
申请号：US12852191
申请日：2010-08-06
申请人： Seiji Funaba , Yasuo Noto , Masashige Tsuji
发明人： Seiji Funaba , Yasuo Noto , Masashige Tsuji
IPC分类号： H02J7/00 , H02M3/06 , H01G9/00
CPC分类号： H02J7/0031 , B60K6/445 , H02J7/0077 , H02J7/045 , H02J7/047 , H02J9/002 , H02M1/36 , H02M2001/322 , Y02T10/6239
摘要： A discharge circuit for a DC power supply smoothing capacitor that is used in a power conversion device that supplies DC power via a switch to the DC power supply smoothing capacitor and an inverter, includes; a resistor that discharges charge in the capacitor; a switch connected in series with the resistor, that either passes or intercepts discharge current flowing from the capacitor to the resistor; a measurement circuit that measures a terminal voltage of the capacitor; and a control circuit that controls continuity and discontinuity of the switch; wherein the control circuit, after having made the switch continuous and starting discharge of the capacitor by the resistor, if a terminal voltage of the capacitor as measured by the measurement circuit exceeds a voltage decrease characteristic set in advance, makes the switch discontinuous and stops discharge by the resistor.
摘要翻译：包括：用于直流电源平滑电容器的放电电路，其用于通过开关向直流电源平滑电容器和逆变器提供直流电力的电力转换装置; 放电电容器中的电荷的电阻器; 与电阻器串联的开关，其通过或截止从电容器流向电阻器的放电电流; 测量电容器的端电压的测量电路; 以及控制电路，其控制开关的连续性和不连续性; 其中，所述控制电路在使所述开关连续地通过所述电阻器连续地开始所述电容器的放电之后，如果由所述测量电路测量的所述电容器的端子电压超过预先设定的电压降低特性，则使所述开关不连续并停止放电由电阻器。

40. 发明授权

US07889584B2 Semiconductor memory device having input first-stage circuit 有权
标题翻译：具有输入第一级电路的半导体存储器件
公开(公告)号：US07889584B2
公开(公告)日：2011-02-15
申请号：US11580275
申请日：2006-10-13
申请人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
发明人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
IPC分类号： G11C7/02
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.
摘要翻译：本发明的半导体存储器件基于预定的参考电压确定信号的逻辑电平。并且存储器件具有输入具有参考电压的参考信号的输入端子，连接到输入端子的低通滤波器，用于通过参考信号的参考电压的分量并消除不期望的高频分量，以及一个或多个输入第一级电路分别连接低通滤波器的输出和具有待确定逻辑电平的信号。在存储器件中，低通滤波器至少在工作时钟的频率上具有预定的衰减。

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